IP Library Granted Patent US 8,004,027
Granted Patent B2
US 8,004,027 · App. 12/204,856 · Granted Aug 23, 2011

Image sensor and manufacturing method thereof

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Quick Facts
Patent No.
US 8,004,027
App. No.
12/204,856
Granted
Aug 23, 2011
Kind
B2
Abstract

Provided is an image sensor. The image sensor comprises an interlayer dielectric, lines, and a crystalline semiconductor layer including photodiodes and a device isolation region. The interlayer dielectric can be formed on a first substrate comprising a readout circuitry. The lines pass through the interlayer dielectric to connect with the readout circuitry, and each line is formed according to unit pixel. The crystalline semiconductor layer can be bonded on the interlayer dielectric including the lines. The photodiodes, formed inside the crystalline semiconductor layer, are electrically connected with the lines. The device isolation region comprises conductive impurities and is formed inside the crystalline semiconductor layer so that the photodiodes can be separated according to unit pixels.

Claims (47)

1. An image sensor comprising:

a first substrate comprising a readout circuitry;

an interlayer dielectric on the first substrate;

lines passing through the interlayer dielectric to connect with the readout circuitry, the lines being formed for each unit pixel;

a crystalline semiconductor layer on the interlayer dielectric;

photodiodes inside the crystalline semiconductor layer, the photodiodes being electrically connected with the lines; and

a device isolation region comprising conductive impurities, the device isolation region being provided inside the crystalline semiconductor layer so that the photodiodes are separated according to unit pixels.

2. The image sensor according to claim 1 , wherein the readout circuitry comprises an electrical junction region in the first substrate electrically connected to a respective line of the lines, wherein the electrical junction region comprises:

a first conduction type ion implantation region in the first substrate; and

a second conduction type ion implantation region on the first conduction type ion implantation region.

3. The image sensor according to claim 2 , further comprising a first conduction type connection region electrically connected with the respective line on the electrical junction region.

4. The image sensor according to claim 2 , further comprising a first conduction type connection region electrically connected with the respective line at one side of the electrical junction region.

5. The image sensor according to claim 1 , wherein a potential difference is provided between a source and a drain of a transistor of the readout circuitry.

6. The image sensor according to claim 5 , wherein the transistor comprises a transfer transistor, and an ion implantation concentration of the source of the transistor is smaller than an ion implantation concentration of a floating diffusion region at the drain of the transistor.

7. The image sensor according to claim 1 , further comprising:

a passivation layer formed of a dielectric on the photodiode, wherein the passivation layer comprises a trench selectively exposing the photodiode; and

an upper electrode on the passivation layer and connected with the photodiode through the trench.

8. The image sensor according to claim 1 , wherein the photodiode comprises:

a first impurity region in a portion of the crystalline semiconductor layer, the first impurity region being connected with the lines; and

a second impurity region on the first impurity region.

9. The image sensor according to claim 8 , wherein the device isolation region and the second impurity region are formed of the same material.

10. The image sensor according to claim 8 , further comprising an ohmic contact layer under the first impurity region, the ohmic contact layer being formed of high concentration n-type impurities.

11. A method for manufacturing an image sensor according to claim 1 , the method comprising:

forming the readout circuitry on the first substrate;

forming the interlayer dielectric on the first substrate;

forming a line connected with the readout circuitry in the interlayer dielectric;

preparing a second substrate comprising the crystalline semiconductor layer;

forming the photodiodes inside the crystalline semiconductor layer;

implanting conductive impurities into the crystalline semiconductor layer to form the device isolation region such that the photodiodes are separated according to unit pixels;

bonding the first substrate and the second substrate so that the line of the first substrate is electrically connected with one of the photodiodes of the crystalline semiconductor layer; and

removing a portion of the second substrate such that the crystalline semiconductor layer remains on the first substrate.

12. The method according to claim 11 , wherein the forming of the readout circuitry comprises forming an electrical junction region in the first substrate, wherein the forming of the electrical junction region comprises:

forming a first conduction type ion implantation region in the first substrate; and

forming a second conduction type ion implantation region on the first conduction type ion implantation region.

13. The method according to claim 12 , further comprising forming a first conduction type connection region in the first substrate connected with the line on the electrical junction region.

14. The method according to claim 13 , wherein the forming of the first conduction type connection region is performed after a contact etch for the line.

15. The method according to claim 12 , further comprising forming a first conduction type region in the first substrate connected with the line at one side of the electrical junction region.

16. The method according to claim 11 , further comprising:

forming a passivation layer on the photodiode;

forming a trench in the passivation layer to selectively expose the photodiode; and

forming an upper electrode in the trench to electrically connect with the photodiode.

17. The method according to claim 16 , wherein the upper electrode contacts a portion of an edge region of the photodiode.

18. The method according to claim 11 , wherein the forming of the photodiodes comprises:

forming a first impurity region inside the crystalline semiconductor layer; and

forming a second impurity region inside the crystalline semiconductor layer.

19. The method according to claim 18 , further comprising forming an ohmic contact layer on the first impurity region.

20. The method according to claim 18 , wherein the second impurity region comprises the same type of conductive impurities as the device isolation region.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041343/0212 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2008
From: HWANG, JOON
To: DONGBU HITEK CO., LTD.
Reel/Frame 021493/0679 →