Granted Patent B2

US 8,044,478 · App. 12/204,902 · Granted Oct 25, 2011

Abstract

Claims (43)

1. An image sensor comprising:

a first substrate comprising a readout circuitry;

an interlayer dielectric on the first substrate, the interlayer dielectric comprising a lower conductive line therein;

a crystalline semiconductor layer on the interlayer dielectric;

a photodiode in the crystalline semiconductor layer, the photodiode comprising a first impurity region and a second impurity region;

a first via hole passing through the crystalline semiconductor layer and the interlayer dielectric to expose the lower conductive line;

a plug inside the first via hole connecting the lower conductive line to the first impurity region, wherein a top surface of the plug is below the second impurity region; and

a device isolation region in the crystalline semiconductor layer, the device isolation region separating the photodiode according to a unit pixel.

2. The image sensor according to claim 1 , further comprising a first passivation layer on the crystalline semiconductor layer.

3. The image sensor according to claim 1 , further comprising a dielectric on the plug, the dielectric filling the first via hole.

4. The image sensor according to claim 1 , wherein the readout circuitry comprises an electrical junction region in the first substrate, wherein the electrical junction region comprises:

a first conduction type ion implantation region in the first substrate; and

a second conduction type ion implantation region on the first conduction type ion implantation region.

5. The image sensor according to claim 4 , further comprising a first conduction type connection region electrically connected with the lower conductive line on the electrical junction region.

6. The image sensor according to claim 5 , wherein the electrical junction region comprises a PNP junction.

7. The image sensor according to claim 1 , wherein the readout circuitry is designed such that a potential difference is generated between a source and a drain of a transistor.

8. The image sensor according to claim 7 , wherein the transistor comprises a transfer transistor, and an ion implantation impurity concentration of the source of the transistor is lower than an ion implantation impurity concentration of a floating diffusion region at the drain of the transistor.

9. The image sensor according to claim 4 , further comprising a first conduction type connection region electrically connected with the lower conductive line at a side of the electrical junction region.

10. A method for manufacturing an image sensor, according to claim 1 , the method comprising:

forming a readout circuitry on a first substrate;

forming an interlayer dielectric comprising a lower conductive line on the first substrate;

forming a second substrate comprising a crystalline semiconductor layer;

forming a photodiode comprising a first impurity region and a second impurity region in the crystalline semiconductor layer;

bonding the interlayer dielectric of the first substrate to the crystalline semiconductor layer of the second substrate such that the crystalline semiconductor layer is on the interlayer dielectric;

separating the second substrate such that the photodiode is exposed on the first substrate;

forming a first via hole passing through the photodiode and the interlayer dielectric to expose the lower conductive line;

forming a plug inside the first via hole so that the plug is connected with the lower conductive line and the first impurity region and a top surface of the plug is below the second impurity region; and

forming a device isolation region in the crystalline semiconductor layer such that the photodiode is separated according to a unit pixel.

11. The method according to claim 10 , further comprising forming a first passivation layer on the crystalline semiconductor layer after separating the second substrate.

12. The method according to claim 10 , wherein the forming of the plug comprises:

removing a portion of the crystalline semiconductor layer and a portion of the interlayer dielectric to form the first via hole exposing the lower conductive line;

filling the first via hole with a metal layer; and

removing a portion of the metal layer to expose the second impurity region at sides in the first via hole.

13. The method according to claim 12 , further comprising filling a remaining area of the first via hole with a dielectric after the forming of the plug.

14. The method according to claim 10 , wherein the device isolation region is formed using a shallow trench isolation process.

15. The method according to claim 10 , wherein the device isolation region is formed using an ion implantation method.

16. The method according to claim 10 , wherein the forming of the readout circuitry on the first substrate comprises forming an electrical junction region in the first substrate, wherein forming of the electrical junction region in the first substrate comprises:

forming a first conduction type ion implantation region in the first substrate; and

forming a second conduction type ion implantation region on the first conduction type ion implantation region.

17. The method according to claim 16 , further comprising forming a first conduction type connection region connected with the lower conductive line on the electrical junction region.

18. The method according to claim 17 , wherein the forming of the first conduction type connection region is performed after performing a contact etch for the lower conductive line.

19. The method according to claim 16 , further comprising forming a first conduction type connection region connected with the lower conductive line at a side of the electrical junction region.

20. The method according to claim 19 , wherein the first conduction type connection region is formed between a device isolation region of the first substrate and the electrical junction region, and contacts the device isolation region of the first substrate and the electrical junction region.

Assignments (7)