Write-pattern determination for maskless lithography

1. A computer-implemented method for generating a write pattern to be used in a maskless-lithography process, comprising:

determining, using the computer, a one-to-one correspondence between pixels in the write pattern and at least a subset of elements in an array of elements in a spatial-light modulator used in the maskless-lithography process, wherein a configuration of the array of elements in the spatial-light modulator specifies a modification of an illumination pattern that provides an image pattern in the maskless-lithography process; and

generating the write pattern, wherein the write pattern includes features corresponding to at least the subset of elements in the spatial-light modulator, wherein the generating is in accordance with a characteristic dimension of an element in the array of elements in the spatial-light modulator and a target pattern that is to be printed on a semiconductor wafer during the maskless-lithography process, and wherein the generating includes an inverse-lithography calculation in which the write pattern at an object plane in the inverse calculation is estimated based on the target pattern at an image plane in the inverse calculation.

2. The method of claim 1 , wherein the spatial-light modulator includes a grid of elements, and wherein the elements are mirrors.

3. The method of claim 1 , wherein the spatial-light modulator modifies a magnitude of an illumination beam during the maskless-lithography process.

4. The method of claim 1 , wherein at least one of the features includes only one pixel, and wherein at least the subset includes only one element.

5. The method of claim 1 , wherein the spatial-light modulator modifies a phase of an illumination beam during the maskless-lithography process.

6. The method of claim 1 , wherein the write pattern includes information specifying settings of the elements to print a printed pattern corresponding to the features on the semiconductor wafer during the maskless-lithography process.

7. The method of claim 1 , wherein the write pattern is to be reduced by a pre-determined demagnification during the maskless-lithography process.

8. The method of claim 7 , wherein the demagnification is at least 100.

9. The method of claim 1 , wherein the generating includes image-based optical proximity correction in which a forward model is used to estimate a printed pattern to be printed on the semiconductor wafer during the maskless-lithography process.

10. The method of claim 1 , wherein the target pattern includes a format that is compatible with GDSII or OASIS.

11. The method of claim 1 , wherein the write pattern corresponds to a complex transmission function that represents a dynamic configuration of the spatial-light modulator.

12. The method of claim 1 , wherein the write pattern corresponds to a complex reflectivity function that represents a dynamic configuration of the spatial-light modulator.

13. The method of claim 1 , wherein the write pattern includes a binary pattern.

14. The method of claim 1 , wherein the write pattern includes a continuous-tone pattern.

15. The method of claim 1 , wherein the generating includes calculating a gradient of a function, wherein the function depends on the write pattern and an estimate of a printed pattern to be printed on a semiconductor wafer during the maskless-lithography process, and wherein the gradient is calculated in accordance with a formula obtained by taking the derivative of the function.

16. A computer-program product for use in conjunction with a computer system, the computer-program product comprising a non-transitory computer-readable storage medium and a computer-program mechanism embedded therein for generating a write pattern to be used in a maskless-lithography process, the computer-program mechanism including:

instructions for determining a one-to-one correspondence between pixels in the write pattern and at least a subset of elements in an array of elements in a spatial-light modulator used in the maskless-lithography process, wherein a configuration of the array of elements in the spatial-light modulator specifies a modification of an illumination pattern that provides an image pattern in the maskless-lithography process; and

instructions for generating the write pattern, wherein the write pattern includes features corresponding to at least the subset of elements in the spatial-light modulator, wherein the generating is in accordance with a characteristic dimension of an element in the array of elements in the spatial-light modulator and a target pattern that is to be printed on a semiconductor wafer during the maskless-lithography process, and wherein the generating includes an inverse-lithography calculation in which the write pattern at an object plane in the inverse calculation is estimated based on the target pattern at an image plane in the inverse calculation.

17. A computer system to generate a write pattern to be used in a maskless-lithography process, comprising:

at least one processor;

at least one memory; and

at least one program module, the program module stored in the memory and configured to be executed by the processor, at least the program module including:

instructions for determining a one-to-one correspondence between pixels in the write pattern and at least a subset of elements in an array of elements in a spatial-light modulator used in the maskless-lithography process, wherein a configuration of the array of elements in the spatial-light modulator specifies a modification of an illumination pattern that provides an image pattern in the maskless-lithography process; and

instructions for generating the write pattern, wherein the write pattern includes features corresponding to at least the subset of elements in the spatial-light modulator, wherein the generating is in accordance with a characteristic dimension of an element in the array of elements in the spatial-light modulator and a target pattern that is to be printed on a semiconductor wafer during the maskless-lithography process, and wherein the generating includes an inverse-lithography calculation in which the write pattern at an object plane in the inverse calculation is estimated based on the target pattern at an image plane in the inverse calculation.

18. A semiconductor wafer, wherein the semiconductor wafer is produced in a maskless-lithography process that uses a write pattern, wherein the write pattern is determined in a process including the operations of:

determining a one-to-one correspondence between pixels in the write pattern and at least a subset of elements in an array of elements in a spatial-light modulator used in the maskless-lithography process, wherein a configuration of the array of elements in the spatial-light modulator specifies a modification of an illumination pattern that provides an image pattern in the maskless-lithography process; and

generating the write pattern, wherein the write pattern includes features corresponding to at least the subset of elements in the spatial-light modulator, wherein the generating is in accordance with a characteristic dimension of an element in the array of elements in the spatial-light modulator and a target pattern that is to be printed on a semiconductor wafer during the maskless-lithography process, and wherein the generating includes an inverse-lithography calculation in which the write pattern at an object plane in the inverse calculation is estimated based on the target pattern at an image plane in the inverse calculation.

19. A computer system to generate a write pattern to be used in a maskless-lithography process, comprising:

means for computing;

means for storing; and

at least one program module mechanism, the program module mechanism stored in at least the means for storing and configured to be executed by at least the means for computing, at least the program module mechanism including:

instructions for determining a one-to-one correspondence between pixels in the write pattern and at least a subset of elements in an array of elements in a spatial-light modulator used in the maskless-lithography process, wherein a configuration of the array of elements in the spatial-light modulator specifies a modification of an illumination pattern that provides an image pattern in the maskless-lithography process; and

instructions for generating the write pattern, wherein the write pattern includes features corresponding to at least the subset of elements in the spatial-light modulator, wherein the generating is in accordance with a characteristic dimension of an element in the array of elements in the spatial-light modulator and a target pattern that is to be printed on a semiconductor wafer during the maskless-lithography process, and wherein the generating includes an inverse-lithography calculation in which the write pattern at an object plane in the inverse calculation is estimated based on the target pattern at an image plane in the inverse calculation.