Write-pattern determination for maskless lithography

1. An apparatus to print a target pattern on a semiconductor wafer during a maskless-lithography process, comprising:

a dynamic source configured to provide an illumination pattern, wherein the dynamic source is electronically configurable; and

a first spatial-light modulator configured to modify the illumination pattern to produce an image pattern, wherein the modification of the illumination pattern is in accordance with a write pattern that specifies settings of elements in the first spatial-light modulator for at least an exposure of at least a portion of the semiconductor wafer during the maskless-lithography process;

wherein the write pattern is compressed using a run-length encoding technique; and

wherein, for at least one linear array of pixels in the write pattern, the run-length encoding technique provides at least one sequence including:

a first number of consecutive first type of pixels in the write pattern;

a first grayscale value for a first transition pixel;

a second number of consecutive second type of pixels in the write pattern;

a second grayscale value for a second transition pixel; and

a third number of consecutive first type of pixels in the write pattern.

2. The apparatus of claim 1 , wherein the dynamic source includes a second spatial-light modulator.

3. The apparatus of claim 1 , wherein settings of the dynamic source and the first spatial-light modulator are selected based on the target pattern.

4. The apparatus of claim 1 , wherein the target pattern includes a format that is compatible with GDSII or OASIS.

5. The apparatus of claim 1 , wherein the dynamic source enables adjustment of the size of an aperture.

6. The apparatus of claim 1 , wherein the dynamic source enables adjustment of the shape of an aperture.

7. The apparatus of claim 1 , wherein the maskless-lithography process includes multiple exposures, and wherein the dynamic source is to be adjusted between at least two of the multiple exposures.

8. The apparatus of claim 1 , wherein the elements in the first spatial-light modulator are arranged in a grid, and wherein the elements are mirrors.

9. The apparatus of claim 1 , wherein the first spatial-light modulator is configured to modify a magnitude of the illumination pattern during the maskless-lithography process.

10. The apparatus of claim 1 , wherein the first spatial-light modulator is configured to modify a phase of the illumination pattern during the maskless-lithography process.

11. The apparatus of claim 1 , wherein the maskless-lithography process includes multiple exposures, and wherein the first spatial-light modulator is to be adjusted between at least two of the multiple exposures.

12. The apparatus of claim 1 , wherein the write pattern includes a binary pattern.

13. The apparatus of claim 1 , wherein the write pattern includes a continuous-tone pattern.

14. A method for providing an image pattern during a maskless-lithography process, comprising:

adjusting a dynamic source to provide an illumination pattern, wherein the dynamic source is electronically configurable; and

configuring a first spatial-light modulator to provide the image pattern by modifying the illumination pattern, wherein modification of the illumination pattern is in accordance with a write pattern that specifies settings of elements in the first spatial-light modulator for at least an exposure of at least a portion of a semiconductor wafer during the maskless-lithography process;

wherein the write pattern is compressed using a run-length encoding technique; and

wherein, for at least one linear array of pixels in the write pattern, the run-length encoding technique provides at least one sequence including:

a first number of consecutive first type of pixels in the write pattern;

a first grayscale value for a first transition pixel;

a second number of consecutive second type of pixels in the write pattern;

a second grayscale value for a second transition pixel; and

a third number of consecutive first type of pixels in the write pattern.

15. An apparatus to print a target pattern on a semiconductor wafer during a maskless-lithography process, comprising:

first means for providing an illumination pattern, wherein the first means includes a dynamic source; and

second means for modifying the illumination pattern, wherein the modification of the illumination pattern is in accordance with a write pattern that specifies settings of the second means for at least an exposure of at least a portion of the semiconductor wafer during the maskless-lithography process;

wherein the write pattern is compressed using a run-length encoding technique; and

wherein, for at least one linear array of pixels in the write pattern, the run-length encoding technique provides at least one sequence including:

a first number of consecutive first type of pixels in the write pattern;

a first grayscale value for a first transition pixel;

a second number of consecutive second type of pixels in the write pattern;

a second grayscale value for a second transition pixel; and

a third number of consecutive first type of pixels in the write pattern.

16. A method for providing a write pattern to a device that is to print a target pattern on a semiconductor wafer during a maskless-lithography process, comprising:

receiving a compressed write pattern at the device;

decoding the compressed write pattern to produce the write pattern; and

adjusting a spatial-light modulator in the device in accordance with the write pattern, wherein the write pattern specifies settings of elements in the spatial-light modulator for at least an exposure of at least a portion of the semiconductor wafer during the maskless-lithography process;

wherein the compressed write pattern is compressed using a run-length encoding technique; and

wherein, for at least one linear array of pixels in the write pattern, the run-length encoding technique provides at least one sequence including:

a first number of consecutive first type of pixels in the write pattern;

a first grayscale value for a first transition pixel;

a second number of consecutive second type of pixels in the write pattern;

a second grayscale value for a second transition pixel; and

a third number of consecutive first type of pixels in the write pattern.

17. The method of claim 16 , wherein the target pattern includes a format that is compatible with GDSII or OASIS.

18. The method of claim 16 , wherein the compressed write pattern is received by the device and the decoding occur concurrently, thereby enabling dynamic adjustment of the spatial-light modulator during the maskless-lithography process.

19. The method of claim 16 , wherein the elements in the spatial-light modulator are arranged in a grid, and wherein the elements are mirrors.

20. The method of claim 16 , wherein the spatial-light modulator modifies a magnitude of an illumination beam during the maskless-lithography process.

21. The method of claim 16 , wherein the spatial-light modulator modifies a phase of an illumination beam during the maskless-lithography process.

22. The method of claim 16 , wherein the maskless-lithography process includes multiple exposures, and wherein the spatial-light modulator is adjusted between at least two of the multiple exposures.

23. The method of claim 16 , wherein the write pattern includes a binary pattern.

24. The method of claim 16 , wherein the first type of pixels correspond to a binary ‘1’ in the write pattern and the second type of pixels correspond to a binary ‘0’ in the write pattern.

25. The method of claim 16 , wherein the first type of pixels correspond to a binary ‘0’ in the write pattern and the second type of pixels correspond to a binary ‘1’ in the write pattern.

26. The method of claim 16 , wherein the linear array corresponds to a row in the write pattern.

27. The method of claim 16 , wherein the linear array corresponds to a column in the write pattern.

28. The method of claim 16 , wherein the write pattern includes a continuous-tone pattern, and wherein the write pattern is compressed using a lossless compression technique.

29. The method of claim 28 , wherein the lossless compression technique includes a Joint Photographic Experts Group (JPEG) compression technique.

30. An apparatus to print a target pattern on a semiconductor wafer during a maskless-lithography process, comprising a spatial-light modulator configured to modify an illumination beam,

wherein the modification of the illumination beam is in accordance with a write pattern that specifies settings of elements in the spatial-light modulator for at least an exposure of at least a portion of the semiconductor wafer during the maskless-lithography process; and

wherein the apparatus is configured to receive a compressed write pattern and to decode the compressed write pattern to produce the write pattern;

wherein the compressed write pattern is compressed using a run-length encoding technique; and

wherein, for at least one linear array of pixels in the write pattern, the run-length encoding technique provides at least one sequence including:

a first number of consecutive first type of pixels in the write pattern;

a first grayscale value for a first transition pixel;

a second number of consecutive second type of pixels in the write pattern;

a second grayscale value for a second transition pixel; and

a third number of consecutive first type of pixels in the write pattern.

31. The apparatus of claim 30 , wherein the compressed write pattern is to be received and the decoding is to occur concurrently, thereby enabling dynamic adjustment of the spatial-light modulator during the maskless-lithography process.

32. An apparatus to print a target pattern on a semiconductor wafer during a maskless-lithography process, comprising a means for modifying an illumination beam,

wherein the modification of the illumination beam is in accordance with a write pattern that specifies settings of the means for at least an exposure of at least a portion of the semiconductor wafer during the maskless-lithography process; and

wherein the apparatus is configured to receive a compressed write pattern and to decode the compressed write pattern to produce the write pattern;

wherein the compressed write pattern is compressed using a run-length encoding technique; and

wherein, for at least one linear array of pixels in the write pattern, the run-length encoding technique provides at least one sequence including:

a first number of consecutive first type of pixels in the write pattern;

a first grayscale value for a first transition pixel;

a second number of consecutive second type of pixels in the write pattern;

a second grayscale value for a second transition pixel; and

a third number of consecutive first type of pixels in the write pattern.

33. A data structure stored in a non-transitory computer-readable memory, comprising a compressed write pattern corresponding to a write pattern, wherein the compressed write pattern specifies settings of elements in a spatial-light modulator for at least an exposure of at least a portion of the semiconductor wafer during a maskless-lithography process;

wherein the compressed write pattern is compressed using a run-length encoding technique; and

wherein, for at least one linear array of pixels in the write pattern, the run-length encoding technique provides at least one sequence including:

a first number of consecutive first type of pixels in the write pattern;

a first grayscale value for a first transition pixel;

a second number of consecutive second type of pixels in the write pattern;

a second grayscale value for a second transition pixel; and

a third number of consecutive first type of pixels in the write pattern.