Method for notch filtering a digital signal, and corresponding electronic device
View Patent ↗An electronic device, includes sigma-delta modulation circuit to operate with a clock signal and having output circuitry to deliver a digital data signal. First circuitry delivers a radiofrequency transposition signal. A notch filter includes radiofrequency digital-to-analog conversion blocks, having first input circuitry coupled to the output circuitry. Second input circuitry receives the radiofrequency transposition signal. Second output circuitry delivers a radiofrequency analog signal. Digital delay circuitry is controlled by the clock signal and includes a delay block between the two first input circuits. The frequency of a notch of the notch filter is related to the value of the delay from the delay block. Summation circuitry sums the radiofrequency signals.
1. An electronic device comprising:
a sigma-delta modulator to generate a digital data signal;
circuitry to generate a radiofrequency (RF) transposition signal;
a notch filter comprising a plurality of digital to analog converters (DACs), each having
a first input to receive a signal based upon the digital data signal,
a second input to receive the RF transposition signal, and
an output to output an analog RF signal;
digital delay circuitry comprising a respective delay block coupled between first inputs of successive pairs of said plurality of DACs so that said notch filter has notches related to a delay value of each delay block; and
a summer to sum the analog RF signals output by said plurality of DACs.
2. An electronic device according to claim 1 , wherein said sigma-delta modulator also generates a clock signal; and wherein said digital delay circuitry is controlled by the clock signal.
3. An electronic device according to claim 1 , wherein said plurality of DACs comprise N identical digital to analog conversion blocks;
and wherein said digital delay circuitry comprises a chain of N−1 delay blocks coupled between said first inputs of successive pairs of N identical digital to analog conversion blocks.
4. An electronic device according to claim 1 , wherein a delay value of said delay block is less than 1/(30*BW), BW being a bandwidth of the analog RF signal.
5. An electronic device according to claim 1 , wherein said digital delay circuitry comprises programmable digital delay circuitry.
6. An electronic device according to claim 1 , realized within an integrated circuit.
7. An electronic device according to claim 1 , wherein said sigma-delta modulator circuit, said circuitry to generate a radiofrequency transposition signal, said notch filter, said digital delay circuitry, and said summer define a wireless apparatus.
8. An integrated circuit comprising:
a sigma-delta modulator to generate a clock signal and a digital data signal;
circuitry to generate a radiofrequency (RF) transposition signal;
a notch filter having a plurality of digital to analog converters (DACs), each having
a first input to receive a signal based upon the digital data signal,
a second input to receive the RF transposition signal, and
an output to output an analog RF signal;
programmable digital delay circuitry controlled by the clock signal and comprising a respective delay block coupled between first inputs of successive pairs of said plurality of DACs so that said notch filter has notches related to a delay value of each delay block; and
a summer to sum the analog RF signals output by said plurality of DACs.
9. An integrated circuit according to claim 8 , wherein said plurality of DACs comprise N identical digital to analog conversion blocks;
and wherein said digital delay circuitry comprises a chain of N−1 delay blocks coupled between said first inputs of successive pairs of N identical digital to analog conversion blocks.
10. An integrated circuit according to claim 8 , wherein a delay value of said delay block is less than 1/(30*BW), BW being a bandwidth of the analog RF signal.
11. A method for notch filtering a digital signal with a notch filter having a notch frequency based upon a delay value, delivered by sigma-delta modulation circuitry, the method comprising:
delaying the digital signal, by the delay value, using a clock signal to obtain at least one delayed digital signal;
processing the digital signal and the delayed digital signal using radiofrequency (RF) transposition circuitry and a plurality of digital to analog converters (DACs) to obtain a plurality of analog RF signals; and
summing the plurality of analog RF signals.
12. A method according to claim 11 , wherein delaying the digital signal comprises delaying the digital signal with a plurality of delay values to obtain a plurality of different delayed digital signals; and wherein processing the digital signal and the delayed digital signal comprises processing the digital signal and the plurality of different delayed digital signals identically using RF transposition circuitry and a plurality of DACs to obtain a plurality of analog RF signals.
13. A method according to claim 11 , wherein the delay value comprises a programmable delay value.