3-D integrated circuit system and method
View Patent ↗A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.
1. A controlled laser crystallization process comprising:
creating a single crystal fabrication region of a second device layer formed from silicon seed of a first device layer;
defining a crystallization area in said single crystal fabrication region, wherein said crystallization area is defined to prevent undesired heat transfer to another layer at a different level; and
applying laser to said crystallization area included in said single crystal fabrication region, wherein said laser is applied in a manner that prevents undesired heat transfer to another layer.
2. A controlled laser crystallization process of claim 1 wherein said amorphous layer is included in said second device layer.
3. A controlled laser crystallization process of claim 1 wherein said crystallization area corresponds to a patterned active area and is formed before application of said laser
4. A controlled laser crystallization process of claim 1 wherein said crystallization area corresponds to a device area.
5. A controlled laser crystallization process of claim 4 wherein said device is a transistor.
6. A controlled laser crystallization process of claim 4 wherein said area is up to 10 square micrometers.
7. A controlled laser crystallization process of claim 1 further comprising:
applying a coat layer before application of said laser; and
removing said coat layer after said application of said laser.
8. A controlled laser crystallization process of claim 1 wherein pattern laser crystallization is utilized.
9. A three dimensional multilayer integrated circuit fabrication method comprising:
forming a first device layer; and
forming a second device layer on top of said first device layer with minimal detrimental heat transfer to said first device layer by utilizing a controlled laser layer crystallization process for re-crystallization, wherein a crystallization area is defined to prevent undesired heat transfer between said first device layer and said second device layer and said crystallization area is included in a single crystal fabrication region of said second device layer formed from silicon seed of said first device layer.
10. Three dimensional multilayer integrated circuit fabrication method of claim 9 wherein said controlled laser layer crystallization process re-crystallizes a single crystal region in said second device layer.
11. A three dimensional multilayer integrated circuit fabrication method of claim 9 wherein said controlled laser layer crystallization process applies heat in a defined area of said second layer without detrimental effects on said first layer.
12. A three dimensional multilayer integrated circuit fabrication method of claim 9 wherein said area is the size of a device.