Parallel data output control circuit and semiconductor device
View Patent ↗A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.
1. A semiconductor device, comprising:
a central processing unit; and
a parallel data output control circuit, comprising:
a digital data generating section that generates digital data;
a temporary storage section capable of storing said digital data in number equivalent to a prescribed number of storage units;
a clock generating section that generates an output control clock; and
a data storing section that stores said digital data, stored into said temporary storage section, by each unit in synchronous with said output control clock, said digital data stored into said data storing section being outputted,
wherein said parallel data output control circuit issues a data transfer request to said central processing unit in accordance with outputting said digital data stored in said data storing section.
2. The semiconductor device according to claim 1 ,
wherein when storage of said digital data in number not exceeding said prescribed number of storage units and not smaller than a prescribed number of units is insufficient, said temporary storage section makes a request of said digital data generating section for outputting said digital data in number equivalent to at least said prescribed number of units.
3. The semiconductor device according to claim 1 , wherein said parallel data output control circuit further comprises
a writing control output section that outputs a writing control signal which indicates a timing for capture of said digital data in synchronous with said output control clock.
4. A semiconductor device, comprising:
a central processing unit;
a parallel data output control circuit; and
a DAC that D/A-converts digital data outputted from said parallel data output control circuit, wherein
said parallel data output control circuit includes:
a digital data generating section that generates said digital data,
a temporary storage section capable of storing said digital data in number equivalent to a prescribed number of storage units,
a clock generating section that generates an output control clock, and
a data storing section that stores said digital data, stored into said temporary storage section, by each unit in synchronous with said output control clock, said digital data stored into said data storing section being outputted; and
said parallel data output control circuit issues a data transfer request to said central processing unit in accordance with outputting said digital data stored in said data storing section.
5. A semiconductor device, comprising:
a CPU;
a data buffer that stores data from said CPU and outputs a request signal to said CPU;
a register that stores an output from said data buffer;
a writing control output section that outputs a writing control signal;
a first external connection terminal group that outputs an output from said register to the outside; and
a second external connection terminal group that outputs said writing control signal from said writing control output section to the outside, wherein
said request signal is outputted when a space is generated in a storage region of said data buffer due to data transmission from said data buffer to said register at prescribed time intervals, and
said writing control signal is outputted from said second external connection terminal group after the lapse of prescribed time from the output of the signal from said first external connection terminal group.