Step-up power supply circuit and stepping-up method

1. A step-up power supply circuit comprising:

a charge pump that connects a capacitor to a DC supply voltage by series-parallel switching, thereby boosting the DC supply voltage by a voltage to which the capacitor is charged; and

a regulator that controls negative feedback of output voltage of said charge pump to a target voltage;

wherein said regulator detects signals indicative of whether the output voltage of said charge pump is equal to or greater than each of a plurality of detection voltages or less than each of the plurality of detection voltages, and subjects the series-parallel switching to PWM control based upon a combination of the detected signals.

2. The circuit according to claim 1 , said detected signals of said regulator is in the form of binary signal, and said combination of the detected signals is in the form of binary values.

3. The circuit according to claim 1 , wherein detection of the output voltage of said charge pump is performed by comparing a divided voltage, which is obtained by voltage-dividing the output voltage, with a reference voltage; and

the comparison of the divided voltage with the reference voltage is performed between a plurality of different voltages and a single voltage constituting the other of the compared values.

4. The circuit according to claim 3 , wherein said regulator includes:

a frequency dividing circuit that generates a frequency-divided clock having a period that is twice that of a boost clock;

a voltage dividing circuit that generates the divided voltage;

a comparator circuit that compares the divided voltage and the reference voltage and outputs a plurality of comparison-result signals;

a selection signal generating circuit that reads in logic of each of the comparison-result signals in synch with an edge of the frequency-divided clock and outputs the binary signals as selection signals;

a duty converting circuit that outputs a plurality of clocks having the same period as that of the boost clock and ON duties that differ from the ON duty of the boost clock;

a selector that selects any one of the plurality of clocks or “H”-level logic as a PWM signal based upon the selection signals; and

a gate circuit that takes the logical AND between the frequency-divided clock and the PWM signal and generating control signals for controlling the series-parallel switching.

5. The circuit according to claim 4 , wherein a plurality of different divided voltages are generated by said voltage dividing circuit and are adopted as the plurality of different voltages; and

said comparator circuit compares the plurality of different divided voltages with a single reference voltage.

6. A method for stepping-up voltage comprising:

providing a voltage step-up circuit including: a charge pump that connects a capacitor to a DC supply voltage by series-parallel switching, thereby boosting the DC supply voltage by a voltage to which the capacitor is charged; and a regulator that controls negative feedback of output voltage of said charge pump to a target voltage;

detecting, by said regulator, signals indicative of whether the output voltage of said charge pump is equal to or greater than each of a plurality of detection voltages or less than each of the plurality of detection voltages, and

subjecting the series-parallel switching to PWM control based upon a combination of the detected signals.

7. The method according to claim 6 , said detected signals of said regulator is in the form of binary signal, and said combination of the detected signals is in the form of binary values.

8. The method according to claim 6 , wherein detection of the output voltage of said charge pump is performed by comparing a divided voltage, which is obtained by voltage-dividing the output voltage, with a reference voltage; and

the comparison of the divided voltage with the reference voltage is performed between a plurality of different voltages and a single voltage constituting the other of the compared values.

9. The circuit according to claim 8 , wherein said regulator performs:

frequency dividing to generate a frequency-divided clock having a period that is twice that of a boost clock;

voltage dividing to generate the divided voltage;

comparing the divided voltage and the reference voltage to output a plurality of comparison-result signals;

generating a selection signal circuit so as to read in logic of each of the comparison-result signals in synch with an edge of the frequency-divided clock to output the binary signals as selection signals;

converting duty to output a plurality of clocks having the same period as that of the boost clock and ON duties that differ from the ON duty of the boost clock;

selecting any one of the plurality of clocks or “H”-level logic as a PWM signal based upon the selection signals; and

taking the logical AND between the frequency-divided clock and the PWM signal and generating control signals for controlling the series-parallel switching.

10. The method according to claim 9 , wherein a plurality of different divided voltages are generated by said voltage dividing and are adopted as the plurality of different voltages; and

said comparator circuit compares the plurality of different divided voltages with a single reference voltage.