Reconfigurable device
Disclosed is a reconfigurable device including at least a bus that mutually connects functional blocks, a configuration information memory disposed corresponding to each of the functional blocks, an error detection circuit that detects an error in the configuration information memory, and a buffer which is on-off controlled based on information stored in the configuration information memory and each of which controls connection between each of the functional blocks and each bus. When an error in the configuration information memory is detected by the error detection circuit, the buffer with an output thereof connected to the bus is set to an off-state, based on a result of error detection.
1. A reconfigurable device comprising:
a configuration information memory that stores information on a device configuration;
a switch including an output coupled to a bus that mutually connects functional blocks;
an error detection circuit that detects an error in said configuration information memory; and
a circuit that sets said switch to an off state, responsive to the error detected by said error detection circuit, and controls the switch to an on-off state based on information stored in the configuration information memory.
2. The reconfigurable device according to claim 1 , further comprising
a plurality of the switches being respectively on-off controlled, based on associated information stored in said configuration information memory,
outputs of the switches being coupled to one or a plurality of the buses, the switches being commonly set to an off state, when the error in said configuration information memory is detected by said error detection circuit.
3. The reconfigurable device according to claim 1 , wherein said configuration information memory includes
a logic circuit that performs control of masking transmission of the information stored in said configuration information memory to a control terminal of said switch, based on the result of an error detection in said configuration information memory by said error detection circuit,
said switch being on-off controlled, based on an output of said logic circuit disposed in said configuration information memory.
4. The reconfigurable device according to claim 3 , further comprising
an error holding circuit that holds an error detection signal output from said error detection circuit,
said logic circuit delivering a value that sets said switch to an off-state to the control terminal of said switch, thereby masking the transmission of the information stored in said configuration information memory to the control terminal of said switch, when an output of said error holding circuit indicates the presence of an error in said configuration information memory.
5. The reconfigurable device according to claim 4 , further comprising
a reset circuit that resets said error holding circuit to an error-free state;
wherein, when an error in said configuration information memory is detected by said error detection circuit and then the error is temporarily held by said error holding circuit, after said error holding circuit is reset to the error-free state, said error holding circuit holds the error even if no error is detected by said error detection circuit, based on the output of the logic circuit disposed in said configuration information memory.
6. The reconfigurable device according to claim 1 , further comprising
a circuit that notifies the error in said configuration information memory to a state transition controller, when an output of said error detection circuit indicates the presence of an error in said configuration information memory and generates a signal for stopping a predetermined operation.
7. The reconfigurable device according to claim 1 , further comprising:
a state transition table that receives a current state and outputs a next state;
a selection circuit that selects the state output from said state transition table, based on an event identification code;
an event occurrence determination circuit that outputs a signal which stops a predetermined operation, when the event identification code indicates a predetermined value, and controls said selection circuit so that said selection circuit selects a predetermined state; and
a circuit that outputs a signal which stops an operation in an active state, when at least one of the signal that stops the operation, from said event occurrence determination circuit, and an error detection signal from said error detection circuit is in the active state.
8. The reconfigurable device according to claim 1 , wherein every physically adjacent bits in said configuration information memory are divided into a plurality of groups; and
the reconfigurable device further comprises
a circuit and performs error detection for each of said groups, as said error detection circuit.
9. The reconfigurable device according to claim 1 , wherein
every physically adjacent bits of memory cells in said configuration information memory are divided into a plurality of groups, a redundant bit being allotted to each of said plurality of groups; and
the reconfigurable device further comprises
a circuit that performs error detection with a redundant bit included therefor, for said each group, as said error detection circuit, and generates an overall error detection result based on results of error detection in said plurality of groups.
10. The reconfigurable device according to claim 1 , wherein the switch comprises a tri-state buffer.
11. The reconfigurable device according to claim 1 , wherein said configuration information memory comprises a redundant bit for an error check.
12. The reconfigurable device according to claim 1 , wherein said configuration information memory comprises a parity bit.
13. The reconfigurable device according to claim 12 , wherein said error detection circuit detects a parity error.
14. The reconfigurable device according to claim 1 , wherein parity is embedded in at least one predetermined bit in said configuration information memory, in advance.
15. The reconfigurable device according to claim 1 , wherein said configuration information memory is disposed corresponding to each of the functional blocks; and
said error detection circuit is disposed corresponding to said each of the functional blocks, and receives an output signal of the configuration information memory corresponding to said error detection circuit.
16. The reconfigurable device according to claim 1 , wherein said buses comprise bidirectional buses disposed between a plurality of the functional blocks disposed in an array form.
17. The reconfigurable device according to claim 1 , wherein the configuration information memory controls the switch to control a masking of transmission of the information stored in the configuration information memory to stop an output of the information stored in the configuration information memory being transmitted to the bus when there is an error detection by the error detection circuit, and
wherein the output from the switch to the bus is based on the information stored in the configuration information memory.
18. The reconfigurable device according to claim 1 , wherein the output of the switch that drives the bus controlled by the configuration information memory in which an error detection has occurred, is forcibly set to a high-impedance state to avoid a conflict of the bus with another bus, coupled to the switch, that mutually connects the functional blocks, and
wherein connections among the functional blocks are reconfigurable.
19. A reconfigurable device comprising:
a configuration information memory that stores information on a device configuration;
a switch including an output coupled to a bus that mutually connects functional blocks;
an error detection circuit that detects an error in said configuration information memory; and
a circuit that sets the output of said switch to a predetermined value, responsive to the error detected by said error detection circuit, and controls the switch to an on-off state based on information stored in the configuration information memory.
20. The reconfigurable device according to claim 19 , wherein
said circuit that sets the output of said switch to the predetermined value device comprises
a logic circuit disposed at a stage preceding to said switch,
said logic circuit receiving a signal to be supplied to an input of said switch and an error detection signal from said error detection circuit,
said logic circuit delivering to said switch the signal to be supplied to the input said switch when the error is not detected by said error detection circuit, and
said logic circuit setting an output thereof to a predetermined value and delivering the output of said predetermined value to the input of said switch when the error is detected by said error detection circuit.
21. The reconfigurable device according to claim 19 , wherein the switch comprises a tri-state buffer.
22. The reconfigurable device according to claim 19 , wherein said configuration information memory comprises a redundant bit for an error check.
23. The reconfigurable device according to claim 19 , wherein said configuration information memory comprises a parity bit.
24. The reconfigurable device according to claim 23 , wherein said error detection circuit detects a parity error.
25. The reconfigurable device according to claim 19 , wherein parity is embedded in at least one predetermined bit in said configuration information memory, in advance.
26. The reconfigurable device according to claim 19 , wherein
said configuration information memory is disposed corresponding to each of the functional blocks; and
said error detection circuit is disposed corresponding to said each of the functional blocks, and receives an output signal of the configuration information memory corresponding to said error detection circuit.
27. The reconfigurable device according to claim 19 , wherein said buses comprise bidirectional buses disposed between a plurality of the functional blocks disposed in an array form.
28. A method of reconfigurable device, the method comprising:
storing, by a configuration information memory, information on a device configuration;
switching, by a buffer including an output terminal coupled to a plurality of buses that mutually connect functional blocks, between an on and off state to control an output, for transmission to the buses;
detecting, by an error detection circuit, an error in the configuration information memory;
controlling, by a circuit, the switching of the buffer to the on and off state based on the information stored in the configuration information memory; and
setting, by the circuit, the buffer to an off state in response to the error detected by the error detection circuit to stop the output to the buses by the buffer.