To prevent the value of a successive approximation register, which should be holding the value of the comparison result, from changing due to noise or the like during the A/D conversion by a successive approximation A/D converter, a detection circuit is arranged on an arbitrary bit of a successive approximation register 5 to detect the change in the value of the bit. The detection circuit detects the change in the value during the period in which the successive approximation register should be holding the data, such as during the period other than the comparison time, and outputs an abnormal conversion detection signal.
1. An A/D converter comprising:
a comparator that compares an analog input voltage and a reference voltage;
a successive approximation register that stores the comparison result of the comparator and that generates comparison codes formed of a plurality of bits based on the comparison result;
a D/A converter that generates a reference voltage for the next comparison based on the comparison codes; and
a detection circuit that detects the change in the value of at least one bit of the comparison codes set in the successive approximation register and that outputs an abnormal conversion detection signal.
2. The A/D converter according to claim 1 , wherein
the detection circuit detects the change in the value of each bit of the comparison codes and outputs the abnormal conversion detection signal when the value of any of the bits has changed.
3. The A/D converter according to claim 1 , wherein
the detection circuit detects whether the value of the arbitrary bit is changed after the comparison result is stored in the at least one bit of the successive approximation register.
4. The A/D converter according to claim 1 , further comprising
a sample-hold circuit that samples the analog input voltage, wherein
the first detection circuit detects whether the value of the at least one bit has changed during the period in which the sample-hold circuit samples the input voltage.
5. The A/D converter according to claim 1 , wherein
the detection circuit is the first detection circuit, and
the A/D converter further comprises a second detection circuit that detects whether the comparison result is stored in order from higher bits to lower bits of the successive approximation register.
6. The A/D converter according to claim 1 , wherein
the successive approximation register responds to the abnormal conversion detection signal to initialize the successive approximation register.
7. The A/D converter according to claim 5 ,
wherein the successive approximation register includes: a plurality of holding circuits that store the comparison result of the comparator and that output comparison codes; and a shift register that generates a storage timing signal for storing the comparison result to each of the holding circuits, and
the first detection circuit detects whether the output of the holding circuits has changed after a desired time has passed after the storage timing signal is supplied to the holding circuits.
8. The A/D converter according to claim 7 , wherein
in the second detection circuit, the shift register detects whether the signal is propagated in order from the holding circuits corresponding to the higher bits of the plurality of holding circuits to the holding circuits corresponding to the lower bits.
9. A successive approximation A/D converter comprising
a detection circuit that detects the change after the data of at least one bit that constitutes the successive approximation register is defined as the result of the successive approximation.
10. An A/D converter comprising:
a successive approximation register; and
a comparator that compares a voltage based on data stored in the register and a sampled input voltage,
the A/D converter defining the content of each bit of the stored data of the register in accordance with the comparison output from the comparator,
the A/D converter further comprising a detection circuit that detects the change after the data of at least the highest bit of the register is defined in accordance with the output of the comparator.
11. The A/D converter according to claim 10 , wherein
the detection circuit detects the change in data of a plurality of bits including the highest bit of the register.
12. The A/D converter according to claim 10 , wherein
the detection circuit also detects the change in data of at least the highest bit during the period in which initial value data is stored in the register and in which the comparator stores the data serving as the result of comparison between the voltage based on the initial value data and the input voltage.