Method and apparatus for decoding memory
View Patent ↗A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.
1. An apparatus comprising:
a thin-film transistor-free address decoder, the decoder comprising one or more diodes in a reverse-biased state; and
a thin-film memory cell, wherein the thin-film transistor-free address decoder is configured to select the thin-film memory cell in response to leakage current from a reverse-biased decoder diode.
2. The apparatus of claim 1 , wherein the leakage current triggers a first ovonic threshold switch (OTS) device and thereby exposes a first terminal of the thin-film memory cell to a first access signal.
3. The apparatus of claim 2 , wherein the leakage current triggers a second OTS device and thereby exposes a second terminal of the thin-film memory cell to a second access signal.
4. The apparatus of claim 2 , wherein the first access signal is a voltage source signal.
5. The apparatus of claim 2 , wherein the first access signal is a current source signal.
6. An apparatus comprising:
a thin-film transistor-free address decoder, the decoder comprising one or more diodes in a reverse-biased state; and
a thin-film memory cell, the thin-film memory cell including a phase-change memory element;
wherein the thin-film transistor-free address decoder is configured to select the thin-film memory cell in response to leakage current from the reverse-biased decoder diodes.
7. An apparatus comprising:
a thin-film transistor-free address decoder, the decoder comprising one or more diodes in a reverse-biased state; and
a thin-film memory cell, the thin-film memory cell including a chalcogenide memory element;
wherein the thin-film transistor-free address decoder is configured to select the thin-film memory cell in response to leakage current from the reverse-biased decoder diodes.
8. The apparatus of claim 7 , wherein the thin-film memory cell includes an ovonic threshold switch (OTS) device in series with the chalcogenide memory element, the OTS device configured as an isolation device.
9. The apparatus of claim 7 , wherein the thin-film memory cell includes a diode in series with the chalcogenide memory element, the diode configured as an isolation device.
10. The apparatus of claim 3 , wherein the first terminal of the thin-film memory cell is configured as a column node shared by a plurality of thin-film memory cells within an array of thin-film memory cells.
11. The apparatus of claim 10 , wherein the second terminal of the thin-film memory cell is configured as a row node shared by a plurality of thin-film memory cells within the array of thin-film memory cells.
12. The apparatus of claim 1 , wherein the thin-film transistor-free address decoder includes a plurality of ovonic threshold switch (OTS) devices configured to provide access to the thin-film memory cell with the leakage current.
13. The apparatus of claim 12 , wherein the leakage current triggers an a first OTS device to expose a first terminal of the selected thin-film memory cell to a first access signal.
14. The apparatus of claim 13 , wherein the leakage current triggers a second OTS device to expose a second terminal of the selected thin-film memory cell to a second access signal.
15. The apparatus of claim 13 , wherein the first access signal is a voltage signal.
16. The apparatus of claim 11 , wherein the thin-film memory cell includes a phase change memory element.
17. The apparatus of claim 16 , wherein the thin-film memory cell includes a chalcogenide memory element.
18. The apparatus of claim 17 , wherein the thin-film memory cell includes an OTS device in series with the chalcogenide memory element, the OTS device configured as an isolation device.
19. The apparatus of claim 13 , wherein the first terminal of the thin-film memory cell is configured as a column node shared by a plurality of thin-film memory cells within an array of thin-film memory cells.
20. The apparatus of claim 19 , wherein the second terminal of the thin-film memory cell is configured as a row node shared by a plurality of thin-film memory cells within the array of thin-film memory cells.
21. A standalone memory device comprising:
thin-film memory cells arranged in a cross-point array; and
thin-film peripheral circuitry including a transistor-free thin-film address decoder configured to access the thin-film memory cells, the thin film address decoder comprising an ovonic threshold switch (OTS) triggered by reverse-biasing a diode that couples an address line to a column line.
22. A standalone memory device comprising:
thin-film memory cells arranged in a cross-point array; and
thin-film peripheral circuitry including a transistor-free thin-film address decoder configured to access the thin-film memory cells, the thin film address decoder comprising an ovonic threshold switch (OTS) triggered by reverse-biasing a diode that couples an address line to a row line.
23. A method comprising:
connecting a plurality of diodes to a row of memory cells within a memory array;
reverse biasing all of the diodes connected to the row; and
employing the reverse-bias current of the diodes to trigger an ovonic threshold switch (OTS) device to thereby access a memory cell within the row of memory cells.
24. The method of claim 23 , further comprising:
connecting a plurality of diodes to a column of memory cells within a memory array;
reverse biasing all of the diodes connected to the column; and employing the reverse-bias current of the diodes to trigger an OTS device to thereby access a memory cell within the column of memory cells.
25. The apparatus of claim 1 , further comprising:
a microprocessor configured to access the thin-film memory cell through the thin-film transistor-free address decoder.