Apparatus and method for multi-level cache utilization

1. A processor-based system, comprising:

a processor;

a system memory coupled to the processor;

a mass storage device;

a multi-level non-volatile cache memory located between the system memory and the mass storage device; and

code stored on the processor-based system to cause the processor-based system to utilize the multi-level non-volatile cache memory,

wherein the multi-level non-volatile cache memory includes:

a first level non-volatile cache memory, the first level non-volatile cache memory having a first set of operating characteristics; and

a second level non-volatile cache memory, the second level non-volatile cache memory having a second set of operating characteristics, wherein the second set of operating characteristics are different from the first set of operating characteristics,

wherein the code is configured to cause the processor-based system to utilize the first level non-volatile cache memory differently from the second level non-volatile cache memory in accordance with the respective first and second set of operating characteristics,

wherein the code is configured to cause the processor-based system to implement a first cache insertion policy for the first level non-volatile cache memory and a second cache insertion policy for the second level non-volatile cache memory, wherein the first cache insertion policy is different from the second cache insertion policy,

and wherein the code is further configured to cause the processor-based system to receive a request for mass storage access, the request requesting information to be accessed on the mass storage device, and to cache the information in one of the first level non-volatile cache memory and the second level non-volatile cache memory in accordance with the respective first and second cache insertion policies.

2. The system of claim 1 , wherein the first level non-volatile cache memory comprises relatively faster cache memory as compared to the second level non-volatile cache memory.

3. The system of claim 2 , wherein the second level non-volatile cache memory comprises relatively higher storage density cache memory as compared to the first level non-volatile cache memory.

4. A non-volatile cache memory, comprising:

a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system; and

a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory,

wherein the multi-level non-volatile cache memory includes:

a first level non-volatile cache memory, the first level non-volatile cache memory having a first set of operating characteristics; and

a second level non-volatile cache memory, the second level nonvolatile cache memory having a second set of operating characteristics, wherein the second set of operating characteristics are different from the first set of operating characteristics,

wherein the controller is configured to utilize the first level non-volatile cache memory differently from the second level non-volatile cache memory in accordance with the respective first and second set of operating characteristics,

wherein the controller is configured to implement a first cache insertion policy for the first level non-volatile cache memory and a second cache insertion policy for the second level non-volatile cache memory, wherein the first cache insertion policy is different from the second cache insertion policy,

and wherein the controller is further configured to receive a request for mass storage access, the request requesting information to be accessed on the mass storage device, and to cache the information in one of the first level non-volatile cache memory and the second level non-volatile cache memory in accordance with the respective first and second cache insertion policies.

5. The system of claim 4 , wherein the second level non-volatile cache memory comprises relatively higher storage density cache memory as compared to the first level non-volatile cache memory.

6. The system of claim 5 , wherein the first level non-volatile cache memory comprises single level cell NAND flash memory and the second level nonvolatile cache memory comprises multi-level cell NAND flash memory.

7. A method of utilizing a non-volatile cache memory, comprising:

locating a multi-level non-volatile cache memory between a system memory and a mass storage device of an electronic system;

providing a first level non-volatile cache memory in the multi-level nonvolatile cache memory, the first level non-volatile cache memory having a first set of operating characteristics;

providing a second level non-volatile cache memory in the multi-level nonvolatile cache memory, the second level non-volatile cache memory having a second set of operating characteristics, wherein the second set of operating characteristics are different from the first set of operating characteristics;

utilizing the first level non-volatile cache memory differently from the second level non-volatile cache memory in accordance with the respective first and second set of operating characteristics;

implementing a first cache insertion policy for the first level non-volatile cache memory;

implementing a second cache insertion policy for the second level nonvolatile cache memory, wherein the first cache insertion policy is different from the second cache insertion policy;

receiving a request for mass storage access, the request requesting information to be accessed on the mass storage device; and

caching the information in one of the first level non-volatile cache memory and the second level non-volatile cache memory in accordance with the respective first and second cache insertion policies.

8. The method of claim 7 , wherein the first level non-volatile cache memory comprises relatively faster cache memory as compared to the second level non-volatile cache memory.

9. The method of claim 8 , wherein the second level non-volatile cache memory comprises relatively higher storage density cache memory as compared to the first level non-volatile cache memory.

10. The method of claim 9 , wherein the first level non-volatile cache memory comprises single level cell NAND flash memory and the second level non-volatile cache memory comprises multi-level cell NAND flash memory.