Method of manufacturing semiconductor device
View Patent ↗Each of channel regions 2 a and 3 b is covered by a gate electrode 6 via a gate insulation film 5 and side wall spacers 9 from its top face to both side faces along an x-direction. In other words, there is no insulation material of an STI element isolation structure 4 on both side faces along the x-direction of each of the channel regions 2 b and 3 b (in a non-contact state), thereby preventing stress in a z-direction from being applied by the STI element isolation structure 4 to each of the channel region 2 b and 3 b.
1. A method of manufacturing a semiconductor device, comprising the steps of:
forming a groove within an element isolation region of a semiconductor substrate;
embedding an insulation material in the groove to form an element isolation structure to thereby define an active region on the semiconductor substrate;
partially removing the insulation material of the element isolation structure to expose a surface layer portion of the active region;
introducing an element into a surface of the element isolation structure;
pattern-forming a gate electrode in such a manner as to cover the surface layer portion from a top face to both side faces thereof via a gate insulation film;
introducing impurities into the active region on both sides of the gate electrode to form a pair of impurity diffused layers; and
performing annealing processing to activate the impurities and relieve compression stress of the element isolation structure.
2. The method of manufacturing a semiconductor device according to claim 1 , wherein, when the gate electrode is formed, a polycrystalline silicon film is formed at a temperature of 700° C. to 1000° C. and is patterned in electrode geometry.
3. The method of manufacturing a semiconductor device according to claim 2 , wherein in a case of manufacturing a P-type MOS transistor,
prior to the formation of the gate insulation film, a mask is formed which exposes portions of the element isolation structure in contact with end faces parallel to the gate length of the active region, and the exposed portions of the surface layer of the element isolation structure are made amorphous using the mask.
4. The method of manufacturing a semiconductor device according to claim 2 , wherein in a case of manufacturing an N-type MOS transistor,
the entire surface layer of the element isolation structure is made amorphous.
5. The method of manufacturing a semiconductor device according to claim 1 , wherein
the transistor structure of an N-type in which the impurity diffused layers are formed by introduction of N-type impurities and the transistor structure of a P-type in which the impurity diffused layers are formed by introduction of P-type impurities, are formed on the same semiconductor substrate.