Semiconductor device and an image processor

1. A data processor on a chip for use with a memory and for encoding a first series of image data and decoding a second series of encoded image data for multi-streams, the data processor comprising:

a central processing unit;

a direct memory access controller,

a first port for inputting the first series of image data;

a second port for inputting the second series of encoded image data;

an interface for data read/write operation from and to a memory area of the memory;

an encoding/decoding circuit which selectively performs encoding of the first series of image data written into the memory area and decoding of the second series of encoded image data; and

a plurality of registers which provide an instruction of processing to the encoding/decoding circuit,

wherein the encoding/decoding circuit performs encoding of the first series of image data and decoding of the second series of encoded image data on a time division basis in each series in accordance with the instruction from the plurality of registers.

2. A data processor according to claim 1 ,

wherein the plurality of registers include an address register to which an address of a memory area is designated for each of the first series of image data and the second series of encoded image data.

3. A data processor according to claim 2 ,

wherein the plurality of registers include a parameter register to which encoding parameters are loaded from the memory area designated by the address register, the parameter register holding encoding parameters to be written into the memory area designated by the address register.

4. A data processor according to claim 1 ,

wherein the plurality of registers include a size register, and the size register is a register to which image size information instructing an image size of the image data series to be encoded to the encoding circuit is set.

5. A data processor according to claim 1 ,

wherein the plurality of registers include a type register, and the type register is a register to which image type information instructing to the encoding/decoding circuit an image type corresponding to a prediction encoding system is set.

6. A semiconductor data processor for a cellular telephone, the semiconductor data processor being for use with a synchronous dynamic random access memory and for encoding a first series of image data and decoding a second series of encoded image data for multi-streams, the semiconductor data processor comprising:

a central processing unit;

a direct memory access controller;

a first port for inputting the first series of image data;

a second port for inputting the second series of encoded image data;

an output port for outputting an image data;

an interface for data read/write operation from and to a memory area of the synchronous dynamic random access memory;

an encoding/decoding circuit which selectively performs encoding of the first series of image data written into the memory area and decoding of the second series of encoded image data; and

a plurality of registers which provide an instruction of processing to the encoding/decoding circuit,

wherein the encoding/decoding circuit performs encoding of the first series of image data and decoding of the second series of encoded image data on a time division basis in each series in accordance with the instruction from the plurality of registers.

7. A semiconductor data processor according to claim 6 ,

wherein the plurality of registers include an address register, and the address register is a register to which an address of a memory area is designated for each of the first series of image data and the second series of encoded image data.

8. A semiconductor data processor according to claim 7 ,

wherein the plurality of registers include a parameter register, and the parameter register is a register to which encoding parameters are loaded from the memory area designated by the address register, the parameter register holding encoding parameters to be written into the memory area designated by the address register.

9. A semiconductor data processor according to claim 6 ,

wherein the plurality of registers include a size register, and the size register is a register to which image size information instructing an image size of the image data series to be encoded is set to the encoding circuit.

10. A semiconductor data processor according to claim 6 ,

wherein the plurality of registers include a type register, and the type register is a register to which image type information instructing to the encoding/decoding circuit an image type corresponding to a prediction encoding system is set.

11. A data processor on a semiconductor chip for a television telephone, the data processor being for use with a synchronous dynamic random access memory and for encoding a first series of image data and decoding a second series of encoded image data for multi-streams, the data processor comprising:

a central processing unit;

a direct memory access controller;

a first port for inputting the first series of image data;

an output port for outputting an image data;

a second port for inputting the second series of encoded image data;

an interface for data read/write operation from and to a memory area of the synchronous dynamic random access memory;

an encoding/decoding circuit which selectively performs encoding of the first series of image data written into the memory area and decoding of the second series of encoded image data; and

a plurality of registers which provide an instruction of processing to the encoding/decoding circuit,

wherein the encoding/decoding circuit performs encoding of the first series of image data and decoding of the second series of encoded image data on a time division basis in each series in accordance with the instruction from the plurality of registers, and

wherein the plurality of registers include:

an address register to which an address of a memory area is designated for each of the first series of image data and the second series of encoded image data,

a parameter register to which encoding parameters are loaded from the memory area designated by the address register, the encoding parameter holding encoding parameters to be written into the memory area designated by the address register,

a size register to which image size information instructing an image size of the image data series to be encoded is set to the encoding circuit, and

a type register to which image type information instructing an image type corresponding to a prediction encoding system to the encoding/decoding circuit is set.

12. A data processor according to claim 3 ,

wherein the plurality of registers include an encoding/decoding register, and the encoding/decoding register is a register to which encoding/decoding control information instruction as to whether encoding or decoding is to be made for the image data series is set.

13. A data processor according to claim 1 ,

wherein the memory is used as an area in which the plurality of image data, the plurality of encoded image data, encoding information used for encoding the plurality of image data series and decoding information used for decoding the plurality of encoded image data series are saved.

14. A data processor according to claim 13 ,

wherein encoding information which is necessary for re-starting next encoding processing is saved in the memory and the decoding information is supplied from the memory to the encoding/decoding circuit when the instruction is changed from an image series to an encoded image series.

15. A semiconductor device for encoding a plurality of image data series and decoding a plurality of encoded image data series, comprising:

a memory used as an area to which the plurality of image data, the plurality of encoded image data, encoding information used for encoding the plurality of image data series and decoding information used for decoding the plurality of encoded image data series are saved;

an interface control circuit which performs data read/write operation from and to a memory area;

an encoding/decoding circuit which selectively performs encoding of image data of one series written into the memory area and decoding of encoded image data of one series; and

a plurality of registers which provide an instruction of processing to the encoding/decoding circuit,

wherein the encoding/decoding circuit performs encoding and decoding of image data of a plurality of series on a time division basis and in each series in accordance with the instruction from the plurality of registers.

16. A semiconductor device according to claim 15 ,

wherein encoding information which is necessary for re-starting next encoding processing is saved in the memory and the decoding information is supplied from the memory to the encoding/decoding circuit when the instruction is changed from an image series to an encoded image series.