IP Library › Granted Patent US 8,049,253
Granted Patent B2
US 8,049,253 · App. 12/216,567 · Granted Nov 1, 2011

Semiconductor device and method for manufacturing the same

Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,049,253
App. No.
12/216,567
Granted
Nov 1, 2011
Kind
B2
Abstract

A semiconductor device and a method for manufacturing a semiconductor device are provided. A semiconductor device comprises a first single-crystal semiconductor layer including a first channel formation region and a first impurity region over a substrate having an insulating surface, a first gate insulating layer over the first single-crystal semiconductor layer, a gate electrode over the first gate insulating layer, a first interlayer insulating layer over the first gate insulating layer, a second gate insulating layer over the gate electrode and the first interlayer insulating layer, and a second single-crystal semiconductor layer including a second channel formation region and a second impurity region over the second gate insulating layer. The first channel formation region, the gate electrode, and the second channel formation region are overlapped with each other.

Claims (20)

1. A method for manufacturing a semiconductor device comprising the steps of:

forming a first damaged region in a first single-crystal semiconductor substrate;

bonding the first single-crystal semiconductor substrate and a substrate having an insulating surface with a bonding layer interposed therebetween;

separating the first single-crystal semiconductor substrate, so that a first single-crystal semiconductor layer is left over the substrate having the insulating surface;

forming a first gate insulating layer over the first single-crystal semiconductor layer;

forming a gate electrode over the first gate insulating layer, wherein the gate electrode overlaps the first single-crystal semiconductor layer;

forming a first interlayer insulating layer over the gate electrode;

planarizing an upper surface of the first interlayer insulating layer;

forming a second gate insulating layer over the gate electrode and the first interlayer insulating layer;

forming a second damaged region in a second single-crystal semiconductor substrate;

bonding the second single-crystal semiconductor substrate and the substrate having the insulating surface with the second gate insulating layer interposed therebetween;

separating the second single-crystal semiconductor substrate, so that a second single-crystal semiconductor layer is left over the second gate insulating layer, wherein the second single-crystal semiconductor layer overlaps the gate electrode and the first single-crystal semiconductor layer,

wherein the gate electrode is in contact with the second gate insulating layer, and

wherein the second gate insulating layer is in contact with the second single-crystal semiconductor layer.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the first damaged region is formed by irradiating the first single-crystal semiconductor substrate with first ions, and wherein the second damaged region is formed by irradiating the second single-crystal semiconductor substrate with second ions.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein each of the bonding layer and the second gate insulating layer is a silicon oxide film.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein each of the bonding layer and the second gate insulating layer is a silicon oxide film, and wherein the silicon oxide film is formed by a chemical vapor deposition method with the use of organic silane gas.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the first interlayer insulating layer includes an organic insulating material.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein a complementary circuit is formed of a first transistor including the first single-crystal semiconductor layer and a second transistor including the second single-crystal semiconductor layer.

7. The method for manufacturing a semiconductor device according to claim 1 , wherein the gate electrode is exposed by planarizing the upper surface of the first interlayer insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2008
From: ISOBE, ATSUO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 021272/0137 →
Priority Claims (1)
JP 2007-181762 · Jul 11, 2007 · national
Continuity (1)
Related Publication 20090014799A1 · Jan 15, 2009