System and method for automatic layout of integrated circuit

1 . An automatic layout apparatus comprising:

a storage device storing a cell library containing therein cell library data; and

a layout tool obtaining from said cell library said cell library data associated with cells to be placed as described in a netlist, to perform automatic placement of said cells to be placed;

wherein said obtained cell library data include layout coordinates of diffusion layers within said cells to be placed, and

wherein said layout tool determines positions of said cells to be placed, referring to said layout coordinates of said diffusion layers.

2 . The automatic layout apparatus according to claim 1 , wherein said layout tool determines said positions of said cells to be placed based on a difference between diffusion layers within cells adjacent in a gate length direction of MOS transistors within said cells adjacent.

3 . The automatic layout apparatus according to claim 2 , wherein said layout tool determines said positions of said cells to be placed based on areas of said diffusion layers within said cells adjacent, in addition to said difference between diffusion layers within cells adjacent.

4 . The automatic layout apparatus according to claim 1 , wherein said obtained cell library data include layout coordinates of gates within said cells to be placed, and

said layout tool determines said positions of said cells to be placed based on said layout coordinates of said gates within said cells to be placed.

5 . The automatic layout apparatus according to claim 1 , further comprising a cell library generator generating said library data within said cell library by using other cell library data which do not include layout coordinates of diffusion layers for cells described therein, and layout data of said diffusion layers of said cells described in said other cell library data.

6 . The automatic layout apparatus according to claim 5 , wherein said other cell library data do not include layout coordinates of gates for cells described therein,

wherein said cell library generator generates said library data by using layout data of said gates of said cells described in said other cell library data.

7 . The automatic layout apparatus according to claim 1 , wherein said layout tool determines positions of first and second cells adjacent in a gate length direction so that a stress exerted to a MOS transistor within said first cell is equal to a stress exerted to a MOS transistor within said second cell.

8 . A layout method comprising:

obtaining from a cell library cell library data associated with cells to be placed as described in a netlist, to perform automatic placement of said cells to be placed, said obtained cell library data including layout coordinates of diffusion layers within said cells to be placed; and

determining positions of said cells to be placed, referring to said layout coordinates of said diffusion layers.

9 . A cell library generator apparatus comprising;

a storage unit for storing: original cell library data which do not include coordinate data of diffusion layers and gates within cells; and layout data of diffusion layers and gates within cells; and

a cell library generator generating modified cell library data from said original cell library data, said cell library generator obtaining said layout data of said diffusion layers and gates within said cells described in said original cell library data to incorporate said obtained layout data into said modified cell library data.