Efficient decoding
View Patent ↗Embodiments of a method and apparatus for decoding signals are disclosed. The method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of decoding the bits using a first component code, and simultaneously executing the first stage of decoding again using a second component code, and executing a second stage of decoding using the first component code. The first and second stages of decoding are used to generate the bit stream. Another method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of N stages for decoding the bits, the first stage using a first of M component codes, and simultaneously executing a plurality of the N stages of decoding, each of the plurality of N stages using a different one of the M component codes. The plurality of N stages of decoding are used to generate the bit stream.
1. A method of decoding signals to generate a received bit stream, comprising:
receiving modulated signals;
generating bits representing the modulated signals, and beliefs representing an associated reliability of each bit;
a bit node computation block receiving the bits and associated beliefs, and generating a plurality of bit node messages;
a plurality of M serially-connected pipeline stages receiving the bit node messages and after M decoding cycles, generating a plurality of check node messages once per decoding cycle, comprising;
for each iteration cycle, each of the M serially-connected pipeline stages performing check node computations using all of J component codes, wherein each one of the M serially-connected pipeline stages performs check node computations once per decoding cycle using a single component code that is different than component codes used for all other of the M serially-connected pipeline stages, wherein J is at least as great as M, and wherein each iteration includes M decoding cycles.
2. The method of claim 1 , further comprising:
every decoding cycle after M decoding cycles, the bit node computation block updating beliefs of the received bits using check node messages of a single one of the component codes per decoding cycle, wherein the single one component of the component codes changes for each decoding cycle according to a specific order of the component codes.
3. The method of claim 1 , further comprising:
every decoding cycle, updating all bit node messages of the received bits using check node to bit node messages of a single one of the component codes per decoding cycle, wherein the single one component of the component codes changes for each decoding cycle according to a specific order of the component codes.
4. The method of claim 1 , further comprising the bit node computation block generating a decoded received bit stream once every N iterations, wherein N is a pre-selected number of iterations.
5. The method of claim 4 , wherein N is dynamically selected depending on whether all parity checks of the component codes are satisfied.
6. The method of claim 1 , wherein the check node computations of each of the M serially-connected pipeline stages includes different functionality than all other of the M serially connected pipeline stages.
7. The method of claim 1 , wherein for each cycle of decoding, each of M−1 of the M serially-connected pipeline stage executing one step of check node computations and providing intermediate results to a next stage of the M serially-connected pipeline stages.
8. The method of claim 1 , wherein for each iteration, each stage of the M serially-connected pipeline stages of decoding using updated bit node messages including all previous iterations.
9. The method of claim 1 , further comprising configuring a first of the M serially-connected pipeline stages with a specific component codes, and configuring a last of the M serially-connected pipeline stages with another specific component code.
10. The method of claim 9 , further comprising:
a first sub-block of the first stage re-ordering bit node to check node messages, enabling processing of the a second sub-block of the first stage to remain static as the first stage cycles through processing using the J component codes.
11. The method of claim 10 , wherein the re-ordering of the bit node to check node messages changes every decoding cycle.
12. The method of claim 1 , wherein column weights of a parity check matrix of the component codes are non-zero.
13. The method of claim 1 , wherein each component code comprises a regular LDPC, and column weights of a parity matrix of the component codes are pre-selected values.
14. The method of claim 13 , wherein the pre-selected values are all the same.
15. The method of claim 14 , wherein hardware implementing the stages includes a repeated structure.
16. The method of claim 1 , wherein a parity check matrix of the component codes has column weights of one.