Method and program for designing semiconductor integrated circuit using peripheral parameter

1. A method of designing a semiconductor integrated circuit comprising:

performing, via a processor, a circuit simulation of a cell with changing a peripheral parameter that specifies a relationship between a layout pattern of said cell and a peripheral pattern around said cell, said peripheral parameter affecting electrical characteristics of said cell;

generating, via the processor, a delay function expressing a delay value of said cell as a function of said peripheral parameter, based on a result of said circuit simulation;

generating, via the processor, a layout data indicating a layout of said semiconductor integrated circuit, based on a cell-based design technique;

referring, via the processor, to said generated layout data to extract said peripheral parameter associated with a target cell included in said semiconductor integrated circuit; and

calculating, via the processor, a delay value of said target cell by using said extracted peripheral parameter and said delay function,

wherein said cell includes a first transistor placed near a boundary of said cell,

wherein a second transistor is supposed to be placed adjacent to said first transistor across said boundary, and said peripheral parameter specifies a relative position of a layout pattern of said second transistor with respect to a layout pattern of said first transistor.

2. The method according to claim 1 ,

wherein said peripheral parameter includes an interval between a gate of said first transistor and a gate of said second transistor.

3. The method according to claim 1 ,

wherein said peripheral parameter includes a width of a device isolation structure between said first transistor and said second transistor.

4. A method of designing a semiconductor integrated circuit comprising:

performing, via a processor, a circuit simulation of a cell with changing a peripheral parameter that specifies a relationship between a layout pattern of said cell and a peripheral pattern around said cell, said peripheral parameter affecting electrical characteristics of said cell;

generating, via the processor, a delay function expressing a delay value of said cell as a function of said peripheral parameter, based on a result of said circuit simulation;

generating, via the processor, a layout data indicating a layout of said semiconductor integrated circuit, based on a cell-based design technique;

referring, via the processor, to said generated layout data to extract said peripheral parameter associated with a target cell included in said semiconductor integrated circuit; and

calculating, via the processor, a delay value of said target cell by using said extracted peripheral parameter and said delay function,

wherein said performing said circuit simulation includes:

performing said circuit simulation with setting said peripheral parameter to a reference value to calculate a reference delay value that is said delay value corresponding to said reference value; and

performing said circuit simulation with changing said peripheral parameter from said reference value to calculate said delay value.

5. The method according to claim 4 ,

wherein said generating said delay function includes:

generating said delay function; and

generating a delay library that provides said reference delay value and said delay function.

6. The method according to claim 5 ,

wherein said calculating said delay value of said target cell includes:

obtaining said reference delay value with reference to said delay library;

calculating, by using said extracted peripheral parameter and said delay function, a delay variation that is variation of said delay value from said reference delay value; and

calculating said delay value of said target cell by adding said delay variation to said reference delay value.

7. The method according to claim 4 ,

wherein said generating said delay function includes:

generating a delay variation function that expresses variation of said delay value from said reference delay value as a function of a difference of said peripheral parameter from said reference value, wherein said delay function is a combination of said reference delay value and said delay variation function; and

generating a delay library that provides said reference delay value and said delay variation function.

8. The method according to claim 7 ,

wherein said calculating said delay value of said target cell includes:

obtaining said reference delay value with reference to said delay library;

calculating, by using a difference of said extracted peripheral parameter from said reference value and said delay variation function, a delay variation that is variation of said delay value from said reference delay value; and

calculating said delay value of said target cell by adding said delay variation to said reference delay value.

9. A design program recorded on a non transitory computer-readable medium that, when executed, causes a computer to perform a method of designing a semiconductor integrated circuit, the method comprising:

performing a circuit simulation of a cell with changing a peripheral parameter that specifies a relationship between a layout pattern of said cell and a peripheral pattern around said cell, said peripheral parameter affecting electrical characteristics of said cell;

generating a delay function expressing a delay value of said cell as a function of said peripheral parameter, based on a result of said circuit simulation;

generating a layout data indicating a layout of said semiconductor integrated circuit, based on a cell-based design technique;

referring to said generated layout data to extract said peripheral parameter associated with a target cell included in said semiconductor integrated circuit; and

calculating a delay value of said target cell by using said extracted peripheral parameter and said delay function,

wherein said cell includes a first transistor placed near a boundary of said cell,

wherein a second transistor is supposed to be placed adjacent to said first transistor across said boundary, and said peripheral parameter specifies a relative position of a layout pattern of said second transistor with respect to a layout pattern of said first transistor.

10. A delay calculation program recorded on a non transistory computer-readable medium that, when executed, causes a computer to perform a method of calculating a delay value of a cell based on a layout data of a semiconductor integrated circuit, the method comprising:

reading a delay library from a memory device, wherein said delay library provides a delay function expressing a delay value of a cell as a function of a peripheral parameter that specifies a relationship between a layout pattern of said cell and a peripheral pattern around said cell, said peripheral parameter affecting electrical characteristics of said cell;

referring to said layout data to extract said peripheral parameter associated with a target cell included in said semiconductor integrated circuit; and

calculating a delay value of said target cell by using said extracted peripheral parameter and said delay function,

wherein said cell includes a first transistor placed near a boundary of said cell,

wherein a second transistor is supposed to be placed adjacent to said first transistor across said boundary, and said peripheral parameter specifics a relative position of a layout pattern of said second transistor with respect to a layout pattern of said first transistor.