Method and program for designing semiconductor integrated circuit
View Patent ↗A design method for an LSI includes: generating a delay library for use in a statistical STA, wherein the delay library provides a delay function that expresses a cell delay value as a function of model parameters of a transistor; generating a layout data; and calculating a delay value of a target cell based on the delay library and the layout data. The calculating includes: referring to the layout data to extract a parameter specifying a layout pattern around a target transistor; modulating model parameters of the target transistor such that the characteristics corresponding to the extracted parameter is obtained in a circuit simulation; calculating, by using the delay function, a reference delay value of the target cell; and calculating, by using the delay function and the modulation amount of the model parameter, a delay variation from the reference delay value depending on the modulation amount.
1. A method of designing a semiconductor integrated circuit comprising:
generating, by a processor, a delay library for use in a statistical static timing analysis, wherein said delay library provides a delay function that expresses a delay value of a cell as a function of a model parameter of a transistor in said cell;
generating a layout data indicating a layout of said semiconductor integrated circuit; and
calculating a delay value of a target cell included in said semiconductor integrated circuit, based on said delay library and said layout data,
wherein said calculating the delay value of the target cell comprises:
referring to said layout data to extract a parameter that specifies a layout pattern around a target transistor included in said target cell;
modulating a model parameter of said target transistor such that a characteristic of said target transistor corresponding to said extracted parameter is obtained in a circuit simulation;
calculating, by using said delay function, a reference delay value that is a reference of a delay value of said target cell; and
calculating, by using said delay function and the modulation amount of said model parameter in said modulating, a delay variation that is a variation of said delay value of said target cell from said reference delay value and depends on said modulation amount.
2. The method according to claim 1 ,
wherein said parameter includes an interval between a gate of said target transistor and a gate of a peripheral transistor placed adjacent to said target transistor.
3. The method according to claim 1 ,
wherein said parameter includes a width of a device isolation structure between said target transistor and a peripheral transistor placed adjacent to said target transistor.
4. The method according to claim 1 ,
wherein said target transistor is a transistor placed near a boundary of said target cell.
5. The method according to claim 1 ,
wherein said delay function is a function of a first model parameter among model parameters of a transistor, and a second model parameter among said model parameters is modulated in said modulating,
wherein said calculating the delay variation comprises:
converting the modulation amount of said second model parameter in said modulating into a modulation amount of said first model parameter; and
calculating said delay variation by using said delay function and said modulation amount of said first model parameter.
6. The method according to claim 5 , further comprising:
performing a circuit simulation of a transistor characteristic to calculate a modulation amount of said first model parameter with which a variation of said transistor characteristic depending on modulation of said second model parameter is obtained; and
generating a conversion function that expresses said calculated modulation amount of said first model parameter as a function of the modulation amount of said second model parameter,
wherein said conversion function is used in said converting the modulation amount of said second model parameter.
7. A design program recorded on a non-transitory computer-readable medium that, when executed, causes a computer to perform a method of designing a semiconductor integrated circuit, the method comprising:
generating a delay library for use in a statistical static timing analysis, wherein said delay library provides a delay function that expresses a delay value of a cell as a function of a model parameter of a transistor in said cell;
generating a layout data indicating a layout of said semiconductor integrated circuit; and
calculating a delay value of a target cell included in said semiconductor integrated circuit, based on said delay library and said layout data,
wherein said calculating the delay value of the target cell comprises:
referring to said layout data to extract a parameter that specifies a layout pattern around a target transistor included in said target cell;
modulating a model parameter of said target transistor such that a characteristic of said target transistor corresponding to said extracted parameter is obtained in a circuit simulation;
calculating, by using said delay function, a reference delay value that is a reference of a delay value of said target cell; and
calculating, by using said delay function and the modulation amount of said model parameter in said modulating, a delay variation that is a variation of said delay value of said target cell from said reference delay value and depends on said modulation amount.
8. A delay calculation program recorded on a non-transitory computer-readable medium that, when executed, causes a computer to perform a method of calculating a delay value of a cell in a semiconductor integrated circuit, the method comprising:
reading a layout data indicating a layout of said semiconductor integrated circuit from a memory device;
reading a delay library for use in a statistical static timing analysis from said memory device, wherein said delay library provides a delay function that expresses a delay value of a cell as a function of a model parameter of a transistor in said cell; and
calculating a delay value of a target cell included in said semiconductor integrated circuit, based on said delay library and said layout data,
wherein said calculating the delay value of the target cell comprises:
referring to said layout data to extract a parameter that specifies a layout pattern around a target transistor included in said target cell;
modulating a model parameter of said target transistor such that a characteristic of said target transistor corresponding to said extracted parameter is obtained in a circuit simulation;
calculating, by using said delay function, a reference delay value that is a reference of a delay value of said target cell; and
calculating, by using said delay function and the modulation amount of said model parameter in said modulating, a delay variation that is a variation of said delay value of said target cell from said reference delay value and depends on said modulation amount.