IP Library Granted Patent US 8,270,812
Granted Patent B2
US 8,270,812 · App. 12/219,251 · Granted Sep 18, 2012

Input-output circuit, recording apparatus and reproduction apparatus for digital video signal

Assignee: Hitachi Consumer Electronics Co., Ltd.
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Quick Facts
Patent No.
US 8,270,812
App. No.
12/219,251
Granted
Sep 18, 2012
Kind
B2
Abstract

A video signal input-output circuit and a recording-reproduction apparatus in which a digitally compressed video signal input in packet form can be recorded and reproduced efficiently and in stable fashion. In this apparatus, a clock reference is detected from a packet signal containing the clock reference and a digitally compressed video signal, a time stamp for a packet is generated using a clock signal in phase with the clock reference and added to the particular packet, and the packet signals with the time stamp added thereto are recorded closely to each other in a data storage element such as a magnetic recording medium. At playback, the packet interval is output by being restored to the original length on the basis of the time stamp added to the packet in store.

Claims (15)

1. An apparatus for reproducing a digitally compressed video signal recorded on a recording medium, comprising:

a reproduction circuit which reproduces a digitally compressed video signal recorded on the recording medium, the digitally compressed video signal being an intermittent input signal in the form of fixed length packets, each fixed length packet having a time stamp, the time stamp indicating an output timing of the fixed length packet;

a memory which stores the fixed length packets reproduced by the reproduction circuit;

a time stamp read circuit which reads the time stamp of the each fixed length packet reproduced by the reproduction circuit;

a local oscillator which generates a clock signal;

a counter which counts the clock signal generated by the local oscillator;

an output circuit which outputs the fixed length packets read from the memory; and

a control circuit which controls the output timing of the output circuit so that the each fixed length packet is outputted when a value of the time stamp of the fixed length packet is matched with a count value counted by the counter.

2. A method for reproducing a digitally compressed video signal recorded on a recording medium, the method comprising the steps of:

reproducing a digitally compressed video signal recorded on the recording medium, the digitally compressed video signal being an intermittent input signal in the form of fixed length packets, each fixed length packet having a time stamp, the time stamp indicating an output timing of the fixed length packet;

storing the reproduced fixed length packets in a memory;

reading a time stamp of the each reproduced fixed length packet;

generating a clock signal;

counting the clock signal;

reading the fixed length packets from the memory and outputting the fixed length packets read from the memory so that the each fixed length packet is outputted when a value of the time stamp of the fixed length packet is matched with a count value of the clock signal.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2018
From: HITACHI MAXELL, LTD.
To: MAXELL, LTD.
Reel/Frame 045142/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2014
From: HITACHI CONSUMER ELECTRONICS CO., LTD.; HITACHI CONSUMER ELECTRONICS CO, LTD.
To: HITACHI MAXELL, LTD.
Reel/Frame 033694/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2010
From: HITACHI, LTD.
To: HITACHI CONSUMER ELECTRONICS CO., LTD.
Reel/Frame 024445/0332 →
Priority Claims (2)
JP 6-264874 · Oct 28, 1994 · national
JP 7-140294 · Jun 7, 1995 · national
Continuity (6)
Continuation 11936852 · Nov 8, 2007
Continuation 10367730 · Feb 19, 2003
Continuation 09455413 · Dec 6, 1999
Division 08972457 · Nov 18, 1997
Division 08547662 · Oct 24, 1995
Related Publication 20090003803A1 · Jan 1, 2009