Class D amplifier

1. A class D amplifier in which first and second output signals, as binary signals, are generated from an input signal, to drive a load connected across first and second output terminals, said class D amplifier comprising:

a pulse generating circuit that generates a pulse width modulated first pulse signal from said input signal, an inverted signal of said first output signal, and said second output signal;

a differential pulse generating circuit that receives said first pulse signal and that generates a second pulse signal by inverting a low level and a high level of said first pulse signal and shifting a resulting pulse signal by a half period of said first pulse signal;

a first pulse amplifier that receives said first pulse signal to generate said first output signal to deliver the generated first output signal to said first output terminal; and

a second pulse amplifier that receives said second pulse signal to generate said second output signal to deliver the generated second output signal to said second output terminal.

2. The class D amplifier according to claim 1 , wherein said pulse generating circuit comprises:

a current supplying circuit that receives a first current corresponding to said input signal and that supplies a second current which is positive or negative in accordance with a level of an inverted signal of said first output signal, a third current which is positive or negative in accordance with a level of said second output signal, and a fourth current which is positive or negative in accordance with a level of a rectangular-shaped signal;

a first capacitive device charged and discharged by said first, second, third and fourth currents; and

a first comparator that compares a voltage of said first capacitive device to a reference voltage to output a result of comparison as said first pulse signal.

3. The class D amplifier according to claim 1 , wherein said differential pulse generating circuit renders a time interval during which said first pulse signal is at a first level a time interval during which said second pulse signal is at a second level in the next period; said differential pulse generating circuit rendering a time interval during which said first pulse signal is at a second level a time interval during which said second pulse signal is at a first level in the next period.

4. The class D amplifier according to claim 2 , wherein said differential pulse generating circuit comprises:

second and third capacitive devices;

a first charging/discharging circuit that charges and discharges said second capacitive device with a constant current;

a second charging/discharging circuit that charges and discharges said third capacitive device with another constant current;

a second comparator that compares a voltage of said second capacitive device to a first preset voltage;

a third comparator that compares a voltage of said third capacitive device to a second preset voltage; and

a control circuit that controls said first and second charging/discharging circuits to generate said second pulse signal based on results of comparison by said second and third comparators,

wherein said control circuit operates by:

setting a voltage of said second capacitive device at said first preset voltage;

causing said second capacitive device to start a charging or a discharging at a first edge of said rectangular-shaped signal;

halting the charging or discharging of said second capacitive device with level transition of said first pulse signal;

causing said second capacitive device to start a charging or a discharging at a second edge of said rectangular-shaped signal opposite in direction to said first edge; and

causing a transition of said second pulse signal from a first level to a second level at a timing when the voltage of said second capacitive device is coincident with said first preset voltage;

said control circuit further operating by:

setting a voltage of said third capacitive device at said second preset voltage;

causing said third capacitive device to start a charging or a discharging at a second edge of said rectangular-shaped signal;

halting the charging or discharging of said third capacitive device with level transition of said first pulse signal;

causing said third capacitive device to start a charging or a discharging at said first edge of said rectangular-shaped signal; and

causing a transition of said second pulse signal from said second level to said first level at a timing when the voltage of said third capacitive device is coincident with said second preset voltage.

5. The class D amplifier according to claim 2 , wherein said differential pulse generating circuit comprises:

second and third capacitive devices;

a first charging/discharging circuit that charges and discharges said second capacitive device with a constant current;

a second charging/discharging circuit that charges and discharges said third capacitive device at another constant current;

a comparator that compares a voltage of said second capacitive device or a voltage of said third capacitive device to a preset voltage;

a selection circuit that selects the voltage of said second capacitive device or the voltage of said third capacitive device to deliver a selected voltage to said comparator; and

a control circuit that controls said first charging/discharging circuit or said second charging/discharging circuit to generate said second pulse signal based on a result of comparison by said comparator,

wherein said control circuit operates by:

setting the voltage of said second capacitive device at said first preset voltage;

causing said second capacitive device to start a charging or a discharging at a first edge of said rectangular-shaped signal;

halting the charging or discharging of said second capacitive device with a level transition of said first pulse signal;

controlling said selection circuit to cause said second capacitive device to start a charging or a discharging at a second edge of said rectangular-shaped signal opposite in direction to said first edge, and to select a voltage of said second capacitive device; and

causing a transition of said second pulse signal from a first level to a second level at a timing when the voltage of said second capacitive device is coincident with said first preset voltage,

said control circuit further operating by:

setting a voltage of said third capacitive device at said preset voltage;

causing said third capacitive device to start a charging or a discharging at a second edge of said rectangular-shaped signal;

halting the charging or discharging of said third capacitive device with a level transition of said first pulse signal;

controlling said selection circuit to cause said third capacitive device to start a charging or a discharging at said first edge of said rectangular-shaped signal, and to select the voltage of said third capacitive device; and

causing a transition of said second pulse signal from said second level to said first level at a timing when the voltage of said third capacitive device is coincident with said second preset voltage.

6. A class D amplifier, comprising:

an input terminal that receives an input signal;

first and second output terminals to which can be connected a load, said first and second output terminals thereby providing binary signals to said connected load, as based on said input signal;

a summing junction comprising a first capacitor; and

a first comparator comparing a voltage at said summing junction with a first reference voltage and providing a first comparator output signal that is used to generate said binary signals at said first and second output terminals,

wherein said summing junction sums currents from:

said input signal;

an inverted signal from said first output terminal;

a non-inverted signal from said second output terminal; and

a signal oscillator outputting a rectangular-shaped signal.

7. The class D amplifier of claim 6 , further comprising a differential pulse generating circuit that receives said first comparator output signal and generates a signal provided to said second output terminal.

8. The class D amplifier of claim 7 , said differential pulse generating circuit further receiving as inputs:

a second reference voltage;

a third reference voltage; and

an output voltage from said signal oscillator.

9. The class D amplifier of claim 8 , said differential pulse generating circuit comprising:

a second capacitor;

a third capacitor;

a second comparator;

a third comparator;

a first charging/discharging circuit that charges and discharges said second capacitor with a first constant current; and

a second charging/discharging circuit that charges and discharges said third capacitor with a second constant current,

wherein said second comparator compares said second reference voltage to a voltage on said second capacitor and said third compares said third reference voltage to a voltage on said third capacitor.

10. The class D amplifier of claim 9 , said differential pulse generating circuit further comprising a control circuit receiving as inputs:

said first comparator output signal;

an output from said second comparator;

an output from said third comparator; and

said output voltage from said signal oscillator.

11. The class D amplifier of claim 10 , wherein said control circuit:

sets the voltage of said second capacitor at a first preset voltage;

causes said second capacitor to start a charging or a discharging at a first edge of said rectangular-shaped signal from said signal oscillator;

halts the charging or discharging of said second capacitor device with a level transition of said first pulse signal;

controls said selection circuit to cause said second capacitor to start a charging or a discharging at a second edge of said rectangular-shaped signal opposite in direction to said first edge, and to select a voltage of said second capacitive device; and

causes a transition of said second pulse signal from a first level to a second level at a timing when the voltage of said second capacitive device is coincident with said first preset voltage,

wherein said control circuit further:

sets a voltage of said third capacitor to a preset voltage;

causes said third capacitor to start a charging or a discharging at a second edge of said rectangular-shaped signal;

halts the charging or discharging of said third capacitor with a level transition of said first pulse signal;

controls said selection circuit to cause said third capacitor device to start a charging or a discharging at said first edge of said rectangular-shaped signal, and selects the voltage of said third capacitor; and

causes a transition of said second pulse signal from said second level to said first level at a timing when the voltage of said third capacitive device is coincident with said second preset voltage.

12. The class D amplifier of claim 7 , wherein said differential pulse generating circuit shifts a resulting pulse signal of said first pulse signal by a half period.

13. The class D amplifier of claim 7 , wherein said differential pulse generating circuit renders a time interval during which said first pulse signal is at a first level a time interval during which said second pulse signal is at a second level in the next period; said differential pulse generating circuit rendering a time interval during which said first pulse signal is at a second level a time interval during which said second pulse signal is at a first level in the next period.

14. A class D amplifier, comprising:

an input terminal that receives an input signal;

first and second output terminals to which can be connected a load, said first and second output terminals thereby providing binary signals to said connected load, as based on said input signal; and

a differential pulse generating circuit that shifts an output signal at said second output terminal by a half period relative to an output signal at said first output terminal, the shift ocurring after a pulse width modulation of the input signal.

15. The class D amplifier of claim 14 , further comprising:

a summing junction comprising a capacitor; and

a first comparator comparing a voltage at said summing junction with a first reference voltage and providing a first comparator output signal that is used to generate said binary signals at said first and second output terminals,

wherein said summing junction sums currents from:

said input signal;

an inverted signal from said first output terminal;

a non-inverted signal from said second output terminal; and

a signal oscillator outputting a rectangular-shaped signal.

16. The class D amplifier of claim 15 , further comprising a differential pulse generating circuit that receives said first comparator output signal and generates a signal provided to said second output terminal.

17. The class D amplifier of claim 16 , said differential pulse generating circuit further receiving as inputs:

a second reference voltage;

a third reference voltage; and

an output voltage from said signal oscillator.

18. The class D amplifier of claim 17 , said differential pulse generating circuit comprising:

a second capacitor,

a third capacitor;

a second comparator;

a third comparator;

a first charging/discharging circuit that charges and discharges said second capacitor with a first constant current; and

a second charging/discharging circuit that charges and discharges said third capacitor with a second constant current,

wherein said second comparator compares said second reference voltage to a voltage on said second capacitor and said third compares said third reference voltage to a voltage on said third capacitor.

19. The class D amplifier of claim 18 , said differential pulse generating circuit further comprising a control circuit receiving as inputs:

said first comparator output signal;

an output from said second comparator;

an output from said third comparator; and

said output voltage from said signal oscillator.

20. The class D amplifier of claim 19 , wherein said control circuit:

sets the voltage of said second capacitor at said first preset voltage;

causes said second capacitor to start a charging or a discharging at a first edge of said rectangular-shaped signal from said signal oscillator;

halts the charging or discharging of said second capacitor device with a level transition of said first pulse signal;

controls said selection circuit to cause said second capacitor to start a charging or a discharging at a second edge of said rectangular-shaped signal opposite in direction to said first edge, and to select a voltage of said second capacitive device; and

causes a transition of said second pulse signal from a first level to a second level at a timing when the voltage of said second capacitive device is coincident with said first preset voltage,

wherein said control circuit further:

sets a voltage of said third capacitor said preset voltage;

causes said third capacitor to start a charging or a discharging at a second edge of said rectangular-shaped signal;

halts the charging or discharging of said third capacitor with a level transition of said first pulse signal;

controls said selection circuit to cause said third capacitor device to start a charging or a discharging at said first edge of said rectangular-shaped signal, and selects the voltage of said third capacitor; and

causes a transition of said second pulse signal from said second level to said first level at a timing when the voltage of said third capacitive device is coincident with said second preset voltage.