Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit
The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1 ) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step 2 ) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step 1 by a predetermined coefficient α, and a step (Step 3 ) of calculating a routing difficulty index by dividing the total route length L by the layout area S. Thus, the present invention provides a routing analysis method for an integrated circuit, which, allows calculation of routing difficulty index with high accuracy of prediction.
1. A routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is described hierarchically, the integrated circuit having a first hierarchical module including a second hierarchical module positioned in a lower hierarchy than the first module on the netlist, the method comprising the steps of:
calculating a first routing difficulty index for a whole circuit of the first hierarchical module including the second hierarchical module;
calculating a second routing difficulty index for whole circuit of the second hierarchical module; and
calculating a third routing difficulty index for a circuit portion of the first hierarchical module not including the second hierarchical module using the first and second routing difficulty indices,
wherein the netlist has information on cells constituting the first hierarchical module and the second hierarchical module, and routes connecting the plurality of cells,
wherein the step of calculating the first routing difficulty index includes the step of obtaining a sum of areas of the cells constituting the first hierarchical module, a number of the cells constituting the first hierarchical module or a number of said routes connecting the cells constituting the first hierarchical module from said netlist, to be defined as a first constant,
wherein the step of calculating the second routing difficulty index includes the step of obtaining a sum of areas of the cells constituting the second hierarchical module, a number of the cells constituting the second hierarchical module or a number of the routes connecting the cells constituting the second hierarchical module from said netlist, to be defined as a second constant,
wherein the step of calculating the third routing difficulty index includes the steps of obtaining a first value which is a result of multiplying the first routing difficulty index by a first weighting factor and obtaining a second value which is a result of multiplying the second routing difficulty index by a second weighting factor, and
wherein at least one of calculating steps is performed by a processor of a computer processing device.
2. The routing analysis method according to claim 1 , wherein the netlist has information on cells constituting the first hierarchical module and the second hierarchical module, and routes connecting the plurality of cells, and
wherein the step of calculating the first routing difficulty index further includes the steps of:
calculating a first layout area which is an area of a first layout region by dividing said first constant by a predetermined third constant;
calculating a first total route length by multiplying a predetermined first perimeter length of said first layout region having the first layout area by a predetermined first coefficient; and
dividing the first total route length by the first layout area to obtain the first difficulty index, and
wherein the step of calculating the second routing difficulty index further includes the steps of:
calculating a second layout area which is an area of a second layout region by dividing said first constant by a predetermined fourth constant;
calculating a second total route length by multiplying a predetermined second perimeter length of said second layout region having the second layout are by a predetermined second coefficient; and
dividing the second total route length by the second layout area to obtain the second routing difficulty index.
3. The routing analysis method for an integrated circuit according to claim 1 , wherein the step of calculating the third routing difficulty index further includes:
subtracting at least the second value from the first value to obtain the third routing difficult index.
4. The routing analysis method according to claim 1 , further comprising the step of:
replacing an incomplete portion or a dropout portion with a predetermined cell model before said step of calculating said the first and second routing difficulty indices if said netlist partially includes either one of these portions.