Controller for induction motor

1. A controller for an induction motor comprising:

a storage device which stores values in a plurality of addresses;

a first phase first counter configured to transit circularly among first to N-th states;

a first phase second counter configured to transit circularly among first to fourth states;

a calculating section configured to calculate first calculation values; and

a signal generation section configured to generate first pulse width modulation (PWM) signals for controlling an inverter and synchronous interruption signals at constant time pitch such that pulse widths of said first PWM signals are adjusted based on said first calculation values respectively,

wherein said inverter supplies first electric power to an induction motor based on said first PWM signals,

said first phase first counter transits from one to next of said first to N-th states synchronously to each of said synchronous interruption signals,

said first phase second counter transits from one to next of said first to fourth states synchronously to each transition of said first phase first counter from said N-th state to said first state, and

said calculating section, synchronously to each of said synchronous interruption signals, calculates one of said first calculation values based on said first phase first counter and said first phase second counter from one of said values stored in one of said plurality of addresses.

2. The controller for an induction motor according to claim 1 , further comprising:

an inputting section configured to input a target rotation speed of said induction motor,

wherein said calculating section calculates said first calculation values based on said target rotation speed.

3. The controller for an induction motor according to claim 1 , further comprising:

a second phase first counter configured to transit circularly among first to N-th states;

a second phase second counter configured to transit circularly among first to fourth states;

a third phase first counter configured to transit circularly among first to N-th states; and

a third phase second counter configured to transit circularly among first to fourth states,

wherein said induction motor is a three-phase induction motor,

said calculating section calculates second calculation values and third calculation values,

said signal generation section generates second pulse width modulation (PWM) signals and third pulse width modulation (PWM) signals at said constant time pitch such that pulse widths of said second PWM signals are adjusted based on said second calculation values respectively and pulse widths of said third PWM signals are adjusted based on said third calculation values respectively,

said inverter supplies second electric power to said induction motor based on said second PWM signals and supplies third electric power to said induction motor based on said third PWM signals,

said second phase first counter transits from one to next of said first to N-th states synchronously to each of said synchronous interruption signals,

said second phase second counter transits from one to next of said first to fourth states synchronously to each transition of said second phase first counter from said N-th state to said first state,

said third phase first counter transits from one to next of said first to N-th states synchronously to each of said synchronous interruption signals,

said third phase second counter transits from one to next of said first to fourth states synchronously to each transition of said third phase first counter from said N-th state to said first state,

said calculating section, synchronously to each of said synchronous interruption signals, calculates one of said second calculation values based on said second phase first counter and said second phase second counter from one of values stored in one of said plurality of addresses, and

said calculating section, synchronously to each of said synchronous interruption signals, calculates one of said third calculation values based on said third phase first counter and said third phase second counter from one of values stored in one of said plurality of addresses.

4. The controller for an induction motor according to claim 1 , further comprising:

a first flag configured to transit between first and second states,

wherein said first flag transits from one to another of said first and second states synchronously to each transition of said first phase first counter from said N-th state to said first state,

said plurality of addresses includes first to (N+1)-th addresses,

K is an arbitrary integer from 1 to N,

said calculating section calculates one of said first calculation values by adding a value stored in a K-th address of said storage device to a constant value when said first phase first counter is a K-th state, said first flag is said first state and said first phase second counter is said first state,

said calculating section calculates one of said first calculation values by adding a value stored in a (N+2−K)-th address of said storage device to said constant value when said first phase first counter is said K-th state, said first flag is said second state and said first phase second counter is said second state,

said calculating section calculates one of said first calculation values by subtracting said value stored in said K-th address of said storage device from said constant value when said first phase first counter is said K-th state, said first flag is said first state and said first phase second counter is said third state, and

said calculating section calculates one of said first calculation values by subtracting said value stored in said (N+2−K)-th address of said storage device from said constant value when said first phase first counter is said K-th state, said first flag is said second state and said first phase second counter is said fourth state.

5. The controller for an induction motor according to claim 4 , further comprising:

a second phase first counter configured to transit circularly among first to N-th states;

a second flag configured to transit between first and second states,

a second phase second counter configured to transit circularly among first to fourth states;

a third phase first counter configured to transit circularly among first to N-th states;

a third flag configured to transit between first and second states; and

a third phase second counter configured to transit circularly among first to fourth states,

wherein said induction motor is a three-phase induction motor,

said calculating section calculates second calculation values and third calculation values,

said signal generation section generates second pulse width modulation (PWM) signals and third pulse width modulation (PWM) signals at said constant time pitch such that pulse widths of said second PWM signals are adjusted based on said second calculation values respectively and pulse widths of said third PWM signals are adjusted based on said third calculation values respectively,

said inverter supplies second electric power to said induction motor based on said second PWM signals and supplies third electric power to said induction motor based on said third PWM signals,

said second phase first counter transits from one to next of said first to N-th states synchronously to each of said synchronous interruption signals,

said second flag transit from one to another of said first and second states synchronously to each transition of said second phase first counter from said N-th state to said first state,

said second phase second counter transits from one to next of said first to fourth states synchronously to each transition of said second phase first counter from said N-th state to said first state,

said third phase first counter transits from one to next of said first to N-th states synchronously to each of said synchronous interruption signals,

said third flag transits from one to another of said first and second states synchronously to each transition of said third phase first counter from said N-th state to said first state,

said third phase second counter transits from one to next of said first to fourth states synchronously to each transition of said third phase first counter from said N-th state to said first state,

said calculating section, synchronously to each of said synchronous interruption signals, calculates one of said second calculation values from one of values stored in one of said plurality of addresses,

said calculating section, synchronously to each of said synchronous interruption signals, calculates one of said third calculation values from one of values stored in one of said plurality of addresses,

L is an arbitrary integer from 1 to N,

said calculating section calculates one of said second calculation values by adding a value stored in an L-th address of said storage device to said constant value when said second phase first counter is an L-th state, said second flag is said first state and said second phase second counter is said first state,

said calculating section calculates one of said second calculation values by adding a value stored in a (N+2−L)-th address of said storage device to said constant value when said second phase first counter is said L-th state, said second flag is said second state and said second phase second counter is said second state,

said calculating section calculates one of said second calculation values by subtracting said value stored in said L-th address of said storage device from said constant value when said second phase first counter is said L-th state, said second flag is said first state and said second phase second counter is said third state,

said calculating section calculates one of said second calculation values by subtracting said value stored in said (N+2−L)-th address of said storage-device from said constant value when said second phase first counter is said L-th state, said second flag is said second state and said second phase second counter is said fourth state,

M is an arbitrary integer from 1 to N,

said calculating section calculates one of said third calculation values by adding a value stored in an M-th address of said storage device to said constant value when said third phase first counter is an M-th state, said third flag is said first state and said third phase second counter is said first state,

said calculating section calculates one of said third calculation values by adding a value stored in a (N+2−M)-th address of said storage device to said constant value when said third phase first counter is said M-th state, said third flag is said second state and said third phase second counter is said second state,

said calculating section calculates one of said third calculation values by subtracting said value stored in said M-th address of said storage device from said constant value when said third phase first counter is said M-th state, said third flag is said first state and said third phase second counter is said third state, and

said calculating section calculates one of said third calculation values by subtracting said value stored in said (N+2−M)-th address of said storage device from said constant value when said third phase first counter is said M-th state, said third flag is said second state and said third phase second counter is said fourth state.

6. The controller for an induction motor according to claim 5 , wherein N is a product of a natural number J and 3,

said first phase first counter, said first flag, said first phase second counter, said second phase first counter, said second flag, said second phase second counter, said third phase first counter, said third flag and said third phase second counter are set such that said second phase first counter is a (2J+1)-th state, said second flag is said first state, said second phase second counter is said third state, said third phase first counter is a (J+1)-th state, said third flag is said second state, and said third phase second counter is said second state when said first phase first counter is said first state, said first flag is said first state and said first phase second counter is said first state.

7. A control method for an induction motor comprising:

generating synchronous interruption signals at constant time pitch;

a first phase first counter, synchronously to each of said synchronous interruption signals, transiting from one to next of first to N-th states among which said first phase first counter transits circularly;

a first phase second counter, synchronously to each transition of said first phase first counter from said N-th state to said first state, transiting from one to next of first to fourth states among which said first phase second counter transits circularly;

calculating first calculation values synchronously to said synchronous interruption signals respectively; and

generating first pulse width modulation (PWM) signals for controlling an inverter at said constant time pitch such that pulse widths of said first PWM signals are adjusted based on said first calculation values respectively,

wherein said inverter supplies first electric power to an induction motor based on said first PWM signals, and

one of said first calculation values is calculated based on said first phase first counter and said first phase second counter from a value stored in one of a plurality of addresses of a storage device.

8. The control method for an induction motor according to claim 7 , further comprising:

inputting a target rotation speed of said induction motor,

wherein said first calculation values are calculated based on said target rotation speed.

9. The control method for an induction motor according to claim 7 , further comprising:

a second phase first counter, synchronously to each of said synchronous interruption signals, transiting from one to next of first to N-th states among which said second phase first counter transits circularly;

a second phase second counter, synchronously to each transition of said second phase first counter from said N-th state to said first state, transiting from one to next of first to fourth states among which said second phase second counter transits circularly;

a third phase first counter, synchronously to each of said synchronous interruption signals, transiting from one to next of first to N-th states among which said third phase first counter transits circularly;

a third phase second counter, synchronously to each transition of said third phase first counter from said N-th state to said first state, transiting from one to next of first to fourth states among which said third phase second counter transits circularly;

calculating second calculation values synchronously to said synchronous interruption signals respectively;

calculating third calculation values synchronously to said synchronous interruption signals respectively;

generating second pulse width modulation (PWM) signals at said constant time pitch such that pulse widths of said second PWM signals are adjusted based on said second calculation values respectively; and

generating third pulse width modulation (PWM) signals at said constant time pitch such that pulse widths of said third PWM signals are adjusted based on said third calculation values respectively,

wherein said induction motor is a three-phase induction motor,

said inverter supplies second electric power to said induction motor based on said second PWM signals and supplies third electric power to said induction motor based on said third PWM signals,

one of said second calculation values is calculated based on said second phase first counter and said second phase second counter from a value stored in one of said plurality of addresses, and

one of said third calculation values is calculated based on said third phase first counter and said third phase second counter from a value stored in one of said plurality of addresses.

10. The control method for an induction motor according to claim 7 , further comprising:

a first flag, synchronously to each transition of said first phase first counter from said N-th state to said first state, transiting from one to another of first and second states between which said first flag transits,

wherein said plurality of addresses includes first to (N+1)-th addresses,

K is an arbitrary integer from 1 to N,

one of said first calculation values is calculated by adding a value stored in a K-th address of said storage device to a constant value when said first phase first counter is a K-th state, said first flag is said first state and said first phase second counter is said first state,

one of said first calculation values is calculated by adding a value stored in a (N+2−K)-th address of said storage device to said constant value when said first phase first counter is said K-th state, said first flag is said second state and said first phase second counter is said second state,

one of said first calculation values is calculated by subtracting said value stored in said K-th address of said storage device from said constant value when said first phase first counter is said K-th state, said first flag is said first state and said first phase second counter is said third state, and

one of said first calculation values is calculated by subtracting said value stored in said (N+2−K)-th address of said storage device from said constant value when said first phase first counter is said K-th state, said first flag is said second state and said first phase second counter is said fourth state.

11. The control method for an induction motor according to claim 7 , further comprising:

a second phase first counter, synchronously to each of said synchronous interruption signals, transiting from one to next of first to N-th states among which said second phase first counter transits circularly;

a second flag, synchronously to each transition of said second phase first counter from said N-th state to said first state, transiting from one to another of first and second states between which said second flag transits,

a second phase second counter, synchronously to each transition of said second phase first counter from said N-th state to said first state, transiting from one to next of first to fourth states among which said second phase second counter transits circularly;

a third phase first counter, synchronously to each of said synchronous interruption signals, transiting from one to next of first to N-th states among which said third phase first counter transits circularly;

a third flag, synchronously to each transition of said third phase first counter from said N-th state to said first state, transiting from one to another of first and second states between which said third flag transits,

a third phase second counter, synchronously to each transition of said third phase first counter from said N-th state to said first state, transiting from one to next of first to fourth states among which said third phase second counter transits circularly;

calculating second calculation values synchronously to said synchronous interruption signals respectively;

calculating third calculation values synchronously to said synchronous interruption signals respectively;

generating second pulse width modulation (PWM) signals at said constant time pitch such that pulse widths of said second PWM signals are adjusted based on said second calculation values respectively; and

generating third pulse width modulation (PWM) signals at said constant time pitch such that pulse widths of said third PWM signals are adjusted based on said third calculation values respectively,

wherein said induction motor is a three-phase induction motor,

said inverter supplies second electric power to said induction motor based on said second PWM signals and supplies third electric power to said induction motor based on said third PWM signals,

L is an arbitrary integer from 1 to N,

one of said second calculation values is calculated by adding a value stored in an L-th address of said storage device to said constant value when said second phase first counter is an L-th state, said second flag is said first state and said second phase second counter is said first state,

one of said second calculation values is calculated by adding a value stored in a (N+2−L)-th address of said storage device to said constant value when said second phase first counter is said L-th state, said second flag is said second state and said second phase second counter is said second state,

one of said second calculation values is calculated by subtracting said value stored in said L-th address of said storage device from said constant value when said second phase first counter is said L-th state, said second flag is said first state and said second phase second counter is said third state,

one of said second calculation values is calculated by subtracting said value stored in said (N+2−L)-th address of said storage device from said constant value when said second phase first counter is said L-th state, said second flag is said second state and said second phase second counter is said fourth state,

M is an arbitrary integer from 1 to N,

one of said third calculation values is calculated by adding a value stored in an M-th address of said storage device to said constant value when said third phase first counter is an M-th state, said third flag is said first state and said third phase second counter is said first state,

one of said third calculation values is calculated by adding a value stored in a (N+2−M)-th address of said storage device to said constant value when said third phase first counter is said M-th state, said third flag is said second state and said third phase second counter is said second state,

one of said third calculation values is calculated by subtracting said value stored in said M-th address of said storage device from said constant value when said third phase first counter is said M-th state, said third flag is said first state and said third phase second counter is said third state, and

one of said third calculation values is calculated by subtracting said value stored in said (N+2−M)-th address of said storage device from said constant value when said third phase first counter is said M-th state, said third flag is said second state and said third phase second counter is said fourth state.

12. The control method for an induction motor according to claim 11 , further comprising:

setting said first phase first counter, said first flag, said first phase second counter, said second phase first counter, said second flag, said second phase second counter, said third phase first counter, said third flag and said third phase second counter such that said second phase first counter is a (2J+1)-th state, said second flag is said first state, said second phase second counter is said third state, said third phase first counter is a (J+1)-th state, said third flag is said second state, and said third phase second counter is said second state when said first phase first counter is said first state, said first flag is said first state and said first phase second counter is said first state,

wherein N is a product of J as a natural number and 3.