Memory read control circuit
View Patent ↗A DQS detection circuit 13 detects a preamble of a DQS signal outputted from RAM 11 . An up/down counter 14 counts up a number of clock signals CLK) in a period when an DQSEIN signal showing a continuation length of the DQS signal is active, counts down a number of trailing edges of the DQS signal after the preamble corresponding to a data read request, and detects that a counted value is set to 0. A flip-flop circuit FF 2 makes a mask signal MS) a low level when the counted value is set to 0. An AND circuit AND 2 makes the DQS signal maskable with a mask signal MS.
1. A memory read control circuit, comprising:
a data strobe detection circuit which detects a preamble of a data strobe signal outputted from memory;
a mask circuit which makes the data strobe signal maskable with a mask signal; and
a mask control circuit which inputs information on a data read number relating to a data read request to the memory, decides on the basis of the information on the data read number that the data strobe signal repeated a predetermined number of transitions after the preamble, and performs control to make the mask signal into a masked state,
wherein the mask control circuit performs control to make the mask signal into a masked state on the basis of the data read number coinciding with an edge number of one side of the data strobe signal corresponding to the data read request.
2. The memory read control circuit according to claim 1 , wherein the data read number comprises a read command number.
3. The memory read control circuit according to claim 1 , wherein the mask control circuit includes an up/down counter which counts up or counts down the data read number, and counts down or count up the edge number of one side of the data strobe signal corresponding to the data read request, detects coincidence of the data read number with the edge number of the one side, and performs control to make the mask signal into a masked state on the basis of a detection result of the up/down counter.
4. The memory read control circuit according to claim 3 , wherein the up/down counter counts up or counts down a clock number in a period, when a signal which expresses a continuation length of the data strobe signal is active, instead of counting up or counting down the data read number.
5. The memory read control circuit according to claim 1 , wherein, when the data strobe detection circuit inputs a sampling clock signal and counts a preamble period of the data strobe signal with the sampling clock signal, and a count value becomes a specified value, the data strobe detection circuit starts counting of an edge of one side of the data strobe signal in the mask control circuit.