Synchronous circuit and method for receiving data

1. A synchronous circuit comprising:

a synchronous-word detecting unit receives a baseband received signal including a synchronous word and data for each frame, and detects whether or not the synchronous word is coincided with an expected value in the baseband received signal by using an N-(N is an integer of 2 or larger) phase sampling clock;

a phase information retaining unit retains phase information accumulatively including results detected for a plurality of frames by the synchronous-word detecting unit, and determines a phase to be sampled on the basis of the retained phase information;

a phase selecting unit selects and determines a phase of the sampling clock on the basis of determination by the phase information retaining unit; and

a FIFO buffer samples the data from the baseband received signal, and outputs the sampled data.

2. The synchronous circuit according to claim 1 , wherein the phase information retaining unit retains the phase information for each phase, and determines the phase to be sampled from a normal phase in which the coincidence between the synchronous word and the expected value is detected in the plurality of frames.

3. The synchronous circuit according to claim 2 , wherein the phase information retaining unit determines, as a phase to be sampled, a central phase among a plurality of the normal phases.

4. The synchronous circuit according to claim 2 , wherein the phase information retaining unit determines, as a phase to be sampled, a phase remote from a defective phase in which the coincidence between the synchronous word and the expected value is not detected in a large number of frames.

5. The synchronous circuit according to claim 1 further comprising:

a counter counts a case where the synchronous word is not detected for each phase, on the basis of the result detected by the synchronous-word detecting unit; and

a determinating unit determines a phase to be sampled from a phase where the value of the counter is zero.

6. The synchronous circuit according to claim 5 , wherein the determinating unit determines, as a phase to be sampled, a central phase among a plurality of phases where the value of the counter is zero.

7. The synchronous circuit according to claim 5 , wherein the determinating unit determines, as a phase to be sampled, a phase remote from the phase having the greatest value of the counter.

8. The synchronous circuit according to claim 1 , comprising:

a counter counts a case where the coincidence between the synchronous word and the expected value is detected for each phase, on the basis of the result detected by the synchronous-word detecting unit; and

a determinating unit which determines a phase to be sampled from a phase where the value of the counter is greatest.

9. The synchronous circuit according to claim 8 , wherein the determinating unit determines, as the phase to be sampled, a central phase among a plurality of phases having the greatest value of the counter.

10. The synchronous circuit according to claim 8 , wherein the determinating unit determines, as a phase to be sampled, a phase remote from the phase having the least value of the counter.

11. The synchronous circuit according to claim 1 , wherein the phase selecting unit further determines a phase to be sampled on the basis of a result detected by the synchronous-word detecting unit.

12. A method for receiving data comprising:

receiving a baseband received signal including a synchronous word and data for each frame;

detecting whether or not a synchronous is coincided with an expected value in the baseband received signal by using an N-(N is an integer of 2 or larger) phase sampling clock;

retaining, in a recording area, phase information accumulatively including results detected for a plurality of frames;

selecting a phase to be sampled on the basis of the retained phase information; and

sampling the data from the baseband received signal at the selected phase, and outputting the sampled data.