Circuit design device, circuit design program, and circuit design method
View Patent ↗A circuit design device according to an embodiment of the present invention includes a processor performing operations of: extracting flip-flops each receiving a first clock and a control signal, from flip-flops represented in a first hardware description representing a circuit; generating a second hardware description by replacing the first clock received by each of the extracted flip-flops with a second clock; and generating a third hardware description by inserting, into the second hardware description, data of a control circuit to stop supply of the second clock based on the first clock and the control signal.
1. A circuit design device comprising:
a processor performing operations of
extracting flip-flops each receiving a first clock and a control signal, from flip-flops represented in a first hardware description representing a circuit;
generating a second hardware description by replacing the first clock received by each of the extracted flip-flops with a second clock; and
generating a third hardware description by inserting, into the second hardware description, data of a control circuit to stop supply of the second clock based on the first clock and the control signal.
2. The circuit design device according to claim 1 , further comprising a memory device to store the first hardware description,
wherein the processor reads the first hardware description from the memory device and writes the third hardware description to the memory device.
3. The circuit design device according to claim 1 , wherein the processor inserts, into the second hardware description, data of a delay circuit to delay transmission of the control signal to the control circuit.
4. The circuit design device according to claim 1 , wherein the control signal is a reset signal received by each of the flip-flops represented in the first hardware description.
5. The circuit design device according to claim 4 , wherein the processor extracts flip-flops receiving in common a clock, a reset signal, and a signal level indicating that the received reset signal is active, from the flip-flops represented in the first hardware description.
6. A non-transitory computer-readable medium having computer-readable instructions stored thereon to cause a computer to execute a process comprising:
extracting flip-flops each receiving a first clock and a control signal, from flip-flops represented in a first hardware description representing a circuit;
generating a second hardware description by replacing the first clock received by each of the extracted flip-flops with a second clock; and
generating a third hardware description by inserting, into the second hardware description, data of a control circuit to stop supply of the second clock based on the first clock and the control signal.
7. The non-transitory computer-readable medium according to claim 6 , wherein the process further comprises inserting, into the second hardware description, data of a delay circuit to delay transmission of the control signal to the control circuit.
8. A computer-implemented circuit design method, comprising:
extracting flip-flops each receiving a first clock and a control signal, from flip-flops represented in a first hardware description representing a circuit;
generating a second hardware description by replacing the first clock received by each of the extracted flip-flops with a second clock; and
generating a third hardware description by inserting, into the second hardware description, data of a control circuit to stop supply of the second clock based on the first clock and the control signal.