Apparatus and method for dummy pattern arrangement
View Patent ↗The EB data is separated into an area A and other area. The area A is covered by a recognition layer to which an algorism is linked to form a recognition layer A. For arranging a same dummy pattern for respective areas A, a dummy pattern creation starting point is designated in a common position for each recognition layer A. When there are areas A which have different rotation angles, the recognition layer is created to satisfy a condition that, even if any corner of the area A is designated as the dummy pattern creation starting point, the created dummy pattern becomes an identical arrangement. The sizes DP and gaps GAP of the dummy pattern elements composing the dummy pattern are respectively same in X-direction and Y-direction. The size of the recognition layer A is determined by: a multiple of (DP+GAP)+DP, in X and Y-direction respectively.
1. A dummy pattern arrangement apparatus comprising:
a recognition layer insertion section configured to insert a plurality of recognition layers, each of the plurality of recognition layers covers a specific area on a chip area layout;
a dummy pattern arrangement section configured to designate a corner positioned at a same direction on the chip area layout for each of the plurality of recognition layers as a dummy pattern creation starting point, and create a dummy pattern on the specific area from the dummy pattern creation starting point in EB data (Electron Beam Exposure Data), wherein the dummy pattern is determined to satisfy a condition that a positional relation between the dummy pattern and a circuit formed on the chip area layout in each of the plurality of recognition layers is determined to be same, and wherein the dummy pattern consists of a plurality of dummy pattern elements which are periodically arranged in X-direction and Y-direction,
the X-direction size and the Y-direction size of each of the plurality of dummy pattern elements are same value represented by DP,
the X-direction gap and the Y-direction gap of adjacent elements of the plurality of dummy pattern elements are same value represented by GAP, and
X-direction size X R and Y-direction size Y R of the recognition layer are determined by following:
X R =a ( DP +GAP)+ DP
Y R =b ( DP +GAP)+ DP,
wherein a and b are positive integers, respectively.
2. The dummy pattern arrangement apparatus according to claim 1 , wherein the dummy pattern arrangement section is configured to create a non-specific area dummy pattern which has a different pattern from the dummy pattern on the chip area layout where the recognition layer is not arranged, and wherein the non-specific area is an area outside the specific area.
3. The dummy pattern arrangement apparatus according to claim 1 , further comprising:
a discrete component creation section configured to create data of a discrete component based on circuit information for creating a discrete component, and
the recognition layer insertion section inserts a recognition layer of the plurality of recognition layers in a position covering a discrete component when the specific area exists in a position of the discrete component indicated in the data of discrete component.
4. The dummy pattern arrangement apparatus according to claim 1 , further comprising:
a functional block creation section configured to create data of a functional block based on circuit information for creating a functional block, and
the recognition layer insertion section inserts a recognition layer of the plurality of recognition layers in a position covering a functional block when the specific area exists in a position of the functional block indicated in the data of functional block.
5. The dummy pattern arrangement apparatus according to claim 1 , further comprising:
a 1-chip layout creation section configured to create a 1-chip layout based on circuit information for creating the 1-chip layout, and
the recognition layer insertion section inserts the recognition layer in the specific area after the 1-chip layout is created.
6. The dummy pattern arrangement apparatus according to claim 1 , wherein the recognition layer insertion section inserts the plurality of recognition layers on a chip area layout in GDS (General Data Stream) data, and
the dummy pattern arrangement apparatus further comprises:
a data conversion section configured to convert the GDS data into the EB data.
7. The dummy pattern arrangement apparatus according to claim 1 , wherein the corner is determined dependently on a shape of each of the plurality of recognition layers.
8. The dummy pattern arrangement apparatus according to claim 1 , wherein the recognition layer insertion section discriminates the plurality of recognition layers into a plurality of kinds, and
the dummy pattern arrangement section create the dummy pattern which is determined dependently on a kind of the plurality of kinds of corresponding recognition layer of the plurality of recognition layers.