Non-volatile semiconductor memory device having an erasing gate
A non-volatile semiconductor memory device includes a semiconductor substrate; a floating gate formed above the semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate and the erasing gate; a first silicide film formed on an upper surface of the erasing gate; and a second silicide film formed on an upper surface of the control gate, in which a height of the upper surface of the control gate is flush with/or lower than a height of the upper surface of the erasing gate. With such a device structure, the distance between the upper surface of the erasing gate and the upper surface of the control gate is large, and hence the probability of occurrence of the silicide short between the first silicide film formed on the upper surface of the erasing gate and the second silicide film formed on the upper surface of the control gate may be extremely lowered. Thus, further high speed, operation, miniaturization, and the lower voltage operation of the non-volatile semiconductor memory device having an erasing gate may be achieved.
1 . A non-volatile semiconductor memory device, comprising:
a semiconductor substrate;
a floating gate formed above a gate insulating film covering the semiconductor substrate;
an erasing gate formed above the floating gate intervining a tunnel insulating film therebetween;
a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate and the erasing gate, the floating gate and the erasing gate insulated from the control gate by a sidewall insulating film;
a first silicide film formed on an upper surface of the erasing gate; and
a second silicide film formed on an upper surface of the control gate,
wherein a height of the upper surface of the control gate is flush with/or lower than a height of the upper surface of the erasing gate.
2 . The non-volatile semiconductor memory device according to claim 1 , wherein
the sidewall insulating film is a first sidewall insulating film, and the non-volatile semiconductor memory device further comprises:
a diffusion layer formed on the semiconductor substrate at a position adjacent to the control gate;
a second sidewall insulating film formed over a sidewall of the control gate; and
a third silicide film formed on an upper surface of the diffusion layer.
3 . The non-volatile semiconductor memory device according to claim 2 , wherein, in a cross section including the floating gate and the control gate, the control gate has a corner portion at a side surface on a side in which the diffusion layer is formed.
4 . The non-volatile semiconductor memory device according to claim 2 , wherein
the gate insulating film is a first gate insulating film, and the non-volatile semiconductor memory device further comprises:
a second gate insulating film formed between the semiconductor substrate and the control gate, the second gate insulating film being different from the first gate insulating film.