Semiconductor apparatus
View Patent ↗A semiconductor apparatus capable of simply detecting a crack generated in plural semiconductor chips while the design freedom is improved, includes a first semiconductor chip and a second semiconductor chip that is laminated on the first semiconductor chip, in which a first wiring that is formed along the outer periphery of the first semiconductor chip and a second wiring that is formed along the outer periphery of the second semiconductor chip are connected in series.
1. A semiconductor apparatus comprising:
a first semiconductor chip;
a second semiconductor chip that is laminated on said first semiconductor chip;
a plurality of first electrode pads formed on said first semiconductor chip;
a plurality of second electrode pads formed on said second semiconductor chip;
a first wiring that is coupled to two first electrode pads, which are selected from said plurality of first electrode pads, and formed along the outer periphery of said first semiconductor chip;
a second wiring that is coupled to two second electrode pads, which are selected from the plurality of second electrode pads, and formed along the outer periphery of said second semiconductor chip; and
a third wiring that is coupled to both one of said plurality of first electrode pads being coupled to one end of said first wiring and one of said plurality of second electrode pads being coupled to one end of said second wiring, and couples said first wiring and said second wiring in series.
2. The semiconductor apparatus according to claim 1 , further comprising:
a first terminal;
a second terminal;
a fourth wiring is coupled to both said first terminal and said first electrode pads to which the other end of said first wiring, and
a fifth wiring is coupled to both said second terminal and said second electrode pads to which the other end of said second wiring.
3. The semiconductor apparatus according to claim 2 , wherein said first semiconductor chip is mounted on a substrate that includes said first terminal and said second terminal.
4. The semiconductor apparatus according to claim 3 , wherein said first wiring is formed along the outer peripheries of said first semiconductor chip one or more times, and
said second wiring is formed along the outer peripheries of said second semiconductor chip one or more times.
5. The semiconductor apparatus according to claim 4 , wherein at least one of said first wiring and said second wiring is formed on a layer other than the uppermost layer.
6. The semiconductor apparatus according to claim 5 , wherein any one of the other electrode pad in the two electrode pads coupled to said first wiring and the other electrode pad in the two electrode pads coupled to said second wiring is coupled only to the corresponding wiring.
7. The semiconductor apparatus according to claim 6 ,
wherein said two electrode pads that are coupled to said first wiring are formed along different edges of said first semiconductor chip, and
wherein said two electrode pads that are coupled to said second wiring are formed along different edges of said second semiconductor chip.
8. The semiconductor apparatus according to claim 1 ,
wherein a third semiconductor chip is laminated on said first semiconductor chip or said second semiconductor chip, and
wherein a third wiring being formed along the outer periphery of said third semiconductor chips is coupled in series by said first electrode pads to which the other end of said first wiring or said second electrode pads to which the other end of said second wiring.