Non-volatile semiconductor memory device having an erasing gate

1 . A non-volatile semiconductor memory device, comprising:

a semiconductor substrate;

a floating gate formed above a gate insulating film covering the semiconductor substrate;

an erasing gate formed above the floating gate intervining a tunnel insulating film therebetween;

a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate and the erasing gate, the floating gate and the erasing gate insulated from the control gate by a first sidewall insulating film;

a diffusion layer formed on the semiconductor substrate at a position corresponding to another lateral side of the floating gate and the erasing gate;

a plug formed above the diffusion layer, the plug coupled to the diffusion layer, the floating gate and the erasing, gate insulated from the plug by a second sidewall insulating film;

a first silicide film formed on an upper surface of the erasing gate; and

a second silicide film formed on an upper surface of the plug,

wherein a height of the upper surface of the plug is flush with/or lower than a height of the upper surface of the erasing gate.

2 . The non-volatile semiconductor memory device according to claim 1 , wherein:

adjacent memory cells each share the diffusion layer and the plug; and

the erasing gates and the second sidewall insulating films of the respective adjacent memory cells are formed in symmetrical with respect to the diffusion layer and the plug.

3 . The non-volatile semiconductor memory device according to claim 2 , wherein

the gate insulating film is a first gate insulating film, and the non-volatile semiconductor memory device further comprises:

a second gate insulating film formed between the semiconductor substrate and the control gate, the second gate insulating film being different from the first gate insulating film.