IP Library Granted Patent US 8,468,301
Granted Patent B2
US 8,468,301 · App. 12/227,449 · Granted Jun 18, 2013

Writing of data on an array of storage devices with controlled granularity

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Quick Facts
Patent No.
US 8,468,301
App. No.
12/227,449
Granted
Jun 18, 2013
Kind
B2
Abstract

A disk array control apparatus controls writing of data onto an array of N storage devices such as disk drives, where N is an integer of 3 or greater. Each storage device writes data with a granularity of a sector having a predetermined sector size. The apparatus writes data with a granularity of a transfer unit having a transfer size which is T times the sector size, where T is a plural integer greater than (N−1). The apparatus is allows writing to an array of storage devices for which (N−1) is not a factor of T. In particular, the apparatus divides each transfer unit of data into plural stripes each consisting of a respective plural number of sectors of data having the sector size, the stripes each consisting of at most (N−1) sectors and at least one of the stripes consisting of less than (N−1) sectors, and calculates, in respect of each stripe, a parity sector of parity data. The sectors of data and the parity sector representing the parity of each stripe are written onto different storage devices.

Claims (29)

1. A storage device array control apparatus operable to control writing of data onto an array of N storage devices, where N is an integer of 3 or greater, each storage device being operable to write data with a granularity of a sector having a predetermined sector size, the storage device array control apparatus being operable to control writing of data with a granularity of a transfer unit having a transfer size which is T times the sector size, where T is a plural integer representing the largest amount of data that is transmitted to the storage device array control apparatus at one time, T is greater than (N−1), and (N−1) is not a factor of T, and wherein T is fixed by operating system specifications outside of the control of the storage device array control apparatus, wherein a file to be transmitted to the storage device control apparatus is divided into transfer units,

the storage device array control apparatus being operable to divide each transfer unit of data into plural stripes each consisting of a respective plural number of sectors of data having the sector size by splitting the transfer unit into multiple parts, the stripes having a size S, wherein S is less than T, and to calculate, in respect of each stripe, a parity sector of parity data representing the parity of all sectors of data in the stripe only and not including any sectors of data already stored on a storage device in the array; and

the storage device array control apparatus being operable to cause writing of each sector of data and each parity sector onto respective storage devices in the array, the sectors of data and the parity sector in respect of each stripe being written onto different storage devices.

2. A storage device array control apparatus according to claim 1 , wherein the storage device array control apparatus is operable to cause writing of the sectors of data and the parity sectors to the storage devices at addresses arranged in a pattern which repeats regularly across the storage devices.

3. A storage device array control apparatus according to claim 2 , wherein the storage device array control apparatus has stored therein a mapping between (a) logical block addresses in respect of the data to be written onto the array of storage devices and (b) addresses of the storage devices in accordance with said pattern which repeats regularly across the storage devices, the storage device array control apparatus being operable to cause writing of the sectors of data and the parity sectors to the storage devices at addresses arranged in said pattern by mapping logical block addresses in respect of the data to be written to addresses of the storage devices in accordance with the stored mapping and causing writing of the sectors of data and the parity sectors at the mapped addresses on the storage devices.

4. A storage device array control apparatus according to claim 1 , wherein the storage device array control apparatus is operable to divide each transfer unit of data into plural stripes each consisting of a respective number sectors of data having the sector size, all except one of the stripes consisting of (N−1) sectors and one of the stripes consisting of R sectors where R is the remainder when T is divided by (N−1).

5. A storage device array control apparatus according to claim 1 , wherein T is equal to k·S, where S is an integer less than (N−1) and k is a plural integer, and the storage device array control apparatus is operable to divide each transfer unit of data into k stripes each consisting of S sectors of data having the predetermined sector size.

6. A storage device array control apparatus according to claim 1 , wherein the sector size is 512 bytes.

7. A storage device array control apparatus according to claim 1 , wherein the sector size is 4096 bytes.

8. A storage device array control apparatus according to claim 1 , wherein T is equal to 2 m where M is an integer.

9. A storage device array control apparatus according to claim 7 , wherein T is equal to 8 and N is equal to 4, 6, 7 or 8.

10. A storage device array control apparatus according to claim 1 , wherein the storage devices are disk drives.

11. A storage device array control apparatus according to claim 1 , wherein the storage device array control apparatus includes a data path to which the data to be written is supplied, the data path including a parity calculation circuit operable to perform said dividing of each transfer unit of data and said calculating parity sectors and the data path being switchable to direct the sectors of data and the parity sectors to respective storage devices.

12. A storage device array control apparatus according to claim 11 , wherein the storage device array control apparatus includes a controller which is operable to control the operation of the data path.

13. A storage device array control apparatus according to claim 1 , wherein the storage device array control apparatus comprises an interface for receiving data from a databus, the storage device array control apparatus operable to control writing of data received from the interface.

14. A storage device array control apparatus according to claim 1 , wherein the storage device array control apparatus is formed in a module which is insertable into a computer apparatus.

15. A method of writing data onto an array of N storage devices, where N is an integer of 3 or greater, each storage device being operable to write data with a granularity of a sector having a predetermined sector size, the method being a method of writing data with a granularity of a transfer unit having a transfer size which is T times the sector size, where T is a plural integer representing the largest amount of data that is transmitted to the storage device array control apparatus at one time, T is greater than (N−1), and (N−1) is not a factor of T, and wherein T is fixed by operating system specifications outside of the control of the storage device array control apparatus, wherein a file to be transmitted to the storage device control apparatus is divided into transfer units,

the method comprising;

dividing each transfer unit of data into plural stripes each consisting of a respective plural number of sectors of data having the sector size by splitting the transfer unit into multiple parts, the stripes having a size S, wherein S is less than T;

in respect of each stripe, calculating a parity sector of parity data representing the parity of all the sectors of data in the stripe; and

writing each sector of data and each parity sectors onto a respective storage device in the array with the sectors of data and the parity sectors and the parity sector in respect of each stripe being written onto different storage devices.

16. A method according to claim 15 , wherein the sectors of data and the parity sectors are written onto the storage devices at addresses arranged in a pattern which repeats regularly across the storage devices.

17. A method according to claim 16 , wherein the data to be written onto the array of storage devices has logical block addresses in respect thereof, and the sectors of data and the parity sectors are written onto the storage devices at addresses arranged in said pattern by mapping the logical block addresses to addresses of the storage devices in accordance with said pattern and writing of the sectors of data and the parity sectors at the mapped addresses on the storage devices.

18. A method according to claim 15 , wherein all except one of the stripes consists of (N−1) sectors and one of the stripes consists of R sectors where R is the remainder when T is divided by (N−1).

19. A method according to claim 15 , wherein T is equal to k·S, where S is an integer less than (N−1) and k is a plural integer, and each transfer unit is divided into k stripes each consisting of S sectors of data.

20. A method according to claim 15 , wherein the sector size is 512 bytes.

21. A method according to claim 15 , wherein T is equal to 2 m where M is an integer.

22. A method according to claim 21 , wherein T is equal to 8 and N is equal to 4, 6, 7 or 8.

23. A method according to claim 15 , wherein the storage devices are disk drives.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 034069-0494) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: PLX TECHNOLOGY, INC.
Reel/Frame 037682/0802 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2015
From: PLX TECHNOLOGY, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035615/0767 →
PATENT SECURITY AGREEMENT Recorded Oct 28, 2014
From: PLX TECHNOLOGY, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 034069/0494 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2009
From: OXFORD SEMICONDUCTOR LIMITED
To: PLX TECHNOLOGY, INC.
Reel/Frame 022882/0372 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2009
From: WITHERS, NICHOLAS HUGH
To: OXFORD SEMICONDUCTOR LIMITED
Reel/Frame 022334/0638 →