IP Library Assignment 035615/0767
Patent Assignment
Reel/Frame 035615/0767

Assignment of Assignor's Interest

Recorded: 2015-05-07 Pages: 6
Assignor
PLX TECHNOLOGY, INC.
Executed: 2015-02-02
Assignee
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
NO. 1 YISHUN AVENUE 7, SINGAPORE, 768923, SINGAPORE
Covered Properties (59)
Method and Apparatus for a Fault Tolerant, Software Transparent and High Data Integrity Extension to a Backplane Bus or Interconnect
Patent: 6,091,705 →
Application: 08/771,581 →
Method, System and Apparatus for a Computer Subsystem Interconnection Using a Chain of Bus Repeaters
Patent: 6,581,126 →
Application: 09/315,412 →
System for Transfering Data Using a Usb Host System with a Dedicated Processor
Patent: 7,003,613 →
Application: 09/490,263 →
Universal Serial Bus for Mobile Devices Having Expansion Modules
Patent: 7,028,126 →
Application: 09/667,091 →
Systems and Methods for Batched Usb Data Transfers
Patent: 6,742,076 →
Application: 09/754,828 →
Publication: US 2002/0116565
Multichannel Signal Transmission and Reception for Bluetooth Systems
Patent: 7,145,934 →
Application: 09/798,482 →
Publication: US 2002/0150147
On-Chip Switch Fabric
Patent: 7,039,750 →
Application: 09/912,231 →
Coordination Architecture for Wireless Communication Devices Using Multiple Protocols
Patent: 7,233,602 →
Application: 10/003,703 →
Publication: US 2002/0136233
Collision Rectification in Wireless Communication Devices
Patent: 7,177,294 →
Application: 10/053,860 →
Publication: US 2002/0136183
Centralized Coordination Point for Wireless Communication Devices Using Multiple Protocols
Patent: 7,167,484 →
Application: 10/066,284 →
Publication: US 2002/0136184
Top-Level Controller for Wireless Communication Devices and Protocols
Patent: 6,954,616 →
Application: 10/106,515 →
Publication: US 2002/0173272
Universal Printing System
Patent: 7,212,297 →
Application: 10/164,148 →
Publication: US 2003/0227640
Method and System for Optimizing Polling in Systems Using Negative Acknowledgement Protocols
Patent: 6,898,751 →
Application: 10/209,541 →
Publication: US 2004/0025099
Remotely-Cooperative Scheduling Solution for Moderating Wireless Protocols
Patent: 7,215,659 →
Application: 10/211,954 →
Recognition Scheme for Moderating Wireless Protocols
Patent: 7,277,451 →
Application: 10/211,976 →
Virtual Endpoint for Usb Devices
Patent: 7,222,201 →
Application: 10/338,067 →
Publication: US 2004/0133708
Method, System and Apparatus for a Computer Subsystem Interconnection Using a Chain of Bus Repeaters
Patent: 6,851,009 →
Application: 10/446,402 →
Automatic Embedded Host Configuration System and Method
Patent: 7,287,257 →
Application: 10/680,285 →
Publication: US 2004/0073912
High-Speed Sampling Architectures
Patent: 7,015,842 →
Application: 11/033,661 →
Double-Sampled, Time-Interleaved Analog to Digital Converter
Patent: 7,075,471 →
Application: 11/056,028 →
High-Speed Sampling Architectures
Patent: 7,132,965 →
Application: 11/284,985 →
Publication: US 2006/0152393
System and Method for Usb Controllers
Patent: 7,409,476 →
Application: 11/362,320 →
Random Number Generation
Patent: 7,660,944 →
Application: 11/880,880 →
Publication: US 2008/0022039
Adjustment of Data Storage Capacity Provided by a Storage System
Patent: 9,009,440 →
Application: 11/938,525 →
Publication: US 2009/0125699
Writing of Data on an Array of Storage Devices with Controlled Granularity
Patent: 8,468,301 →
Application: 12/227,449 →
Publication: US 2009/0144497
Circuit for Voltage Controlled Oscillator
Patent: 7,834,709 →
Application: 12/245,078 →
Publication: US 2010/0085127
Dynamic Buffer Pool in Pciexpress Switches
Patent: 7,869,356 →
Application: 12/336,402 →
Publication: US 2009/0154456
Transfer of Commands And Storage Data To A Data Storage Device
Patent: 8,738,812 →
Application: 12/472,901 →
Publication: US 2010/0306417
Supporting Global Input/Output Interconnect Features on Ports of a Midpoint Device
Patent: 8,196,013 →
Application: 12/605,110 →
Publication: US 2011/0099456
USB 3 Bridge With Embedded Hub
Patent: 8,504,755 →
Application: 12/716,584 →
Publication: US 2011/0219163
Generating Unique Random Numbers for Multiple Instantiations
Patent: 8,370,411 →
Application: 12/723,403 →
Publication: US 2011/0225223
Automatic Reference Frequency Compensation
Patent: 8,201,010 →
Application: 12/782,499 →
Publication: US 2011/0289338
Adjusting System Clock to Faster Speed Upon Receiving Mass Storage Command and Back to Lower Speed Upon Completion of All Commands
Patent: 8,417,985 →
Application: 12/782,501 →
Publication: US 2011/0289340
Automated Regression Failure Management System
Patent: 8,145,949 →
Application: 12/816,573 →
Publication: US 2011/0314334
Runtime Reprogramming of a Processor Code Space Memory Area
Application: 12/837,730 →
Publication: US 2012/0017035
Caching Using Virtual Memory
Application: 12/837,778 →
Publication: US 2012/0017039
Automatic Port Accumulation
Patent: 8,327,042 →
Application: 12/875,500 →
Publication: US 2012/0059957
In-Band Generation of Low-Frequency Periodic Signaling
Patent: 8,457,247 →
Application: 12/949,706 →
Publication: US 2012/0128091
Dynamic Buffer Pool in Pciexpress Switches
Patent: 8,797,857 →
Application: 12/957,237 →
Publication: US 2011/0069704
Dynamic Host Clock Compensation
Patent: 8,548,011 →
Application: 12/959,239 →
Publication: US 2012/0140781
Multi-Root Sharing of Single-Root Input/Output Virtualization
Patent: 8,521,941 →
Application: 12/979,904 →
Publication: US 2012/0166690
Parallel Packetized Interconnect with Simplified Data Link Layer
Patent: 8,683,285 →
Application: 12/980,602 →
Publication: US 2012/0173945
Read Control in a Computer I/O Interconnect
Patent: 8,015,330 →
Application: 13/020,702 →
Publication: US 2011/0125947
Three Dimensional Fat Tree Networks
Patent: 8,553,683 →
Application: 13/176,350 →
Publication: US 2013/0010636
Single Pipe Non-Blocking Architecture
Patent: 8,554,976 →
Application: 13/179,074 →
Publication: US 2013/0013840
Sharing Multiple Virtual Functions to a Host Using a Pseudo Physical Function
Patent: 8,645,605 →
Application: 13/212,700 →
Publication: US 2012/0167085
Supporting Global Input/Output Interconnect Features on Ports of a Midpoint Device
Patent: 8,543,890 →
Application: 13/457,275 →
Publication: US 2012/0215948
Automatic Reference Frequency Compensation
Patent: 8,332,681 →
Application: 13/461,358 →
Publication: US 2012/0216066
Multiple Seal-Ring Structure for the Design, Fabrication, and Packaging of Integrated Circuits
Patent: 8,785,246 →
Application: 13/566,332 →
Publication: US 2014/0035106
Pci Express Switch with Logical Device Capability
Patent: 9,141,571 →
Application: 13/624,781 →
Publication: US 2013/0024595
Method and Apparatus for Securing and Segregating Host to Host Messaging on Pcie Fabric
Patent: 8,880,771 →
Application: 13/660,791 →
Publication: US 2014/0122765
Generating Unique Random Numbers for Multiple Instantiations
Application: 13/741,180 →
Publication: US 2013/0132453
Tunneled Window Connection for Programmed Input Output Transfers Over a Switch Fabric
Application: 14/073,491 →
Publication: US 2015/0127878
Switch with Synthetic Device Capability
Patent: 9,223,734 →
Application: 14/106,579 →
Publication: US 2015/0169487
Remote Booting Over Pci Express Using Synthetic Remote Boot Capability
Application: 14/203,149 →
Publication: US 2015/0254082
Multi-Path Id Routing in a Pcie Express Fabric Environment
Application: 14/231,079 →
Publication: US 2014/0237156
Methods and Apparatus for a High Performance Messaging Engine Integrated Within a Pcie Switch
Application: 14/244,634 →
Publication: US 2015/0281126
Multiple Seal-Ring Structure for the Design, Fabrication, and Packaging of Integrated Circuits
Patent: 9,209,137 →
Application: 14/333,348 →
Publication: US 2014/0327115
Unordered Multi-Path Routing in a Pcie Express Fabric Environment
Application: 14/558,404 →
Publication: US 2016/0154756
Related Assignments (18)
Other recorded transfers of the patents in this record — the chain of ownership.
Merger Aug 6, 2014
From: SEBRING SYSTEMS, INC.
To: PLX TECHNOLOGY INC.
Reel/Frame 033480/0323 →
Patent Security Agreement Oct 28, 2014
From: PLX TECHNOLOGY, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 034069/0494 →
Termination and Release of Security Interest in Patent Rights (Releases Rf 034069-0494) Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: PLX TECHNOLOGY, INC.
Reel/Frame 037682/0802 →
Patent Security Agreement Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
Termination and Release of Security Interest in Patents Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
Assignment of Assignor's Interest Sep 24, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047022/0620 →
Corrective Assignment to Correct the Nature of Conveyance and Effective Date Previously Recorded on Reel 047022 Frame 0620. Assignor(S) Hereby Confirms the Merger. Oct 2, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047185/0643 →
Merger Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
Merger Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0026 →
Merger Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
Merger Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047642/0417 →
Corrective Assignment to Correct the Effective Date Previously Recorded on Reel 047185 Frame 0643. Assignor(S) Hereby Confirms the Merger. Oct 26, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047476/0845 →
Corrective Assignment to Correct the Effective Date of Merger Previously Recorded on Reel 047195 Frame 0658. Assignor(S) Hereby Confirms the the Effective Date Is 09/05/2018. Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
Corrective Assignment to Correct the Effective Date of Merger Previously Recorded at Reel: 047185 Frame: 0643. Assignor(S) Hereby Confirms the Corrective Merger. Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047959/0296 →
Corrective Assignment to Correct the Effective Date of Merger Previously Recorded on Reel 047195 Frame 0026. Assignor(S) Hereby Confirms the Merger. Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047477/0423 →
Corrective Assignment to Correct the Execution Date Previously Recorded at Reel: 047196 Frame: 0097. Assignor(S) Hereby Confirms the Merger. Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
Corrective Assignment to Correct the Execution Date of the Merger Previously Recorded on Reel 047642 Frame 0417. Assignor(S) Hereby Confirms the Assignment, Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048521/0395 →
Corrective Assignment to Correct the Error in Recording the Merger Previously Recorded at Reel: 047357 Frame: 0302. Assignor(S) Hereby Confirms the Assignment. Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →