Multiple seal-ring structure for the design, fabrication, and packaging of integrated circuits
View Patent ↗A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.
1. A method of fabricating an electronic device for flexible packaging, comprising:
providing a wafer having an outer seal-ring about a plurality of integrated circuit blocks disposed on the wafer and at least one inner seal-ring about each of at least two subsets of the plurality of integrated circuit blocks, wherein each integrated circuit block is designed to be used either individually or in parallel with one or more other integrated circuit block;
determining whether to package the entire wafer as one unit or to perform die cutting of the wafer to package separate sub-units of the wafer, wherein each subunit has a subset of the plurality of integrated circuit blocks;
if no die cutting is performed, packaging the wafer with all of the plurality of integrated circuit blocks packaged to operate in parallel as a single processing unit with the outer seal-ring encompassing and protecting the plurality of integrated circuit blocks; and
if die cutting is performed, performing die cutting of the wafer into at least two die in which each die has at least one inner seal-ring encompassing and protecting each integrated circuit block of the die, and packaging each cut die, wherein any die having two or more integrated circuit blocks is packaged to operate the two or more integrated circuit blocks in parallel.
2. The method of claim 1 , wherein there is at least one inner seal-ring disposed about each integrated circuit block such that the smallest subunit corresponds to an individual circuit block.
3. The method of claim 2 , wherein the outer seal-ring is separate and distinct from each inner seal-ring.
4. The method of claim 1 , wherein each of the integrated circuit blocks are separated from each other by at least a minimum die saw distance.
5. The method of claim 1 , wherein each integrated circuit block is operable as a system-on-a-chip.
6. The method of claim 1 , in which there is an inner seal-ring about rows of at least two integrated circuit blocks such that the die cutting may be performed to package an individual row of integrated circuit blocks operating in parallel.
7. The method of claim 6 , in which there is an additional inner seal-ring about two rows of integrated circuit blocks, such that the die cutting may be performed to package an individual row as a unit and also a group of rows as a unit.
8. The method of claim 6 , in which there is an integer number N, of integrated circuit blocks and at least one inner seal-ring encompassing each respective one of the N integrated circuit blocks that is not shared with the other integrated circuit blocks.
9. The method of claim 6 , further comprising at least one additional inner seal-ring encompassing a group of at least two integrated circuit blocks.
10. The method of claim 1 , further comprising forming signal connections between individual IC blocks determined to be packaged to operate in parallel.
11. The method of claim 1 , wherein the signal connections are formed by interconnect metal lines.
12. A method of fabricating an electronic device for flexible packaging, comprising:
providing a wafer having an outer seal-ring about a plurality of integrated circuit blocks disposed on the wafer and at least one inner seal-ring about each of at least two subsets of the plurality of integrated circuit blocks, wherein each integrated circuit block is designed to be used either individually or in parallel with one or more other integrated circuit block;
determining whether to package the entire wafer as one unit or to perform die cutting of the wafer to package separate sub-units of the wafer, wherein each subunit has a subset of the plurality of integrated circuit blocks;
fabricating signal interconnects between groups of integrated circuit blocks that operate in parallel after packaging;
if no die cutting is performed, packaging the wafer with all of the plurality of integrated circuit blocks packaged to operate in parallel as a single processing unit with the outer seal-ring encompassing and protecting the plurality of integrated circuit blocks; and
if die cutting is performed, performing die cutting of the wafer into at least two die in which each die has at least one inner seal-ring encompassing and protecting each integrated circuit block of the die, and packaging each cut die, wherein any die having two or more integrated circuit blocks is packaged to operate the two or more integrated circuit blocks in parallel.