Patent Assignment
Reel/Frame 047477/0423
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0026. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER.
Recorded: 2018-11-05
Received: 2018-11-05
Pages: 69
Assignor
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Executed: 2018-09-05
Assignee
AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
1 YISHUN AVENUE 7, SINGAPORE, SGX, 768923, SINGAPORE
Covered Applications
(100)
DISTRIBUTED AVERAGING ANALOG TO DIGITAL CONVERTER TOPOLOGY
App. No. 10/460,622
→
SYSTEMS AND METHODS FOR DIGITAL UPCONVERSION FOR TELEVISION SIGNALS
App. No. 10/452,211
→
CONTENT ADDRESSABLE MEMORY WITH ERROR DETECTION SIGNALING
App. No. 10/453,719
→
VERY DENSE SRAM CIRCUITS
App. No. 10/447,647
→
COMPACT ANALOG-MULTIPLEXED GLOBAL SENSE AMPLIFIER FOR RAMS
App. No. 10/445,772
→
HACKER-PROOF ONE TIME PROGRAMMABLE MEMORY
App. No. 10/438,347
→
DYNAMIC REGISTER WITH IDDQ TESTING CAPABILITY
App. No. 10/436,687
→
METHOD AND APPARATUS FOR A LIMITING AMPLIFIER WITH PRECISE OUTPUT LIMITS
App. No. 10/435,779
→
HIGH VOLTAGE SWITCH CIRCUITRY
App. No. 10/418,254
→
TRANSPARENT CONTINUOUS REFRESH RAM CELL ARCHITECTURE
App. No. 10/414,878
→
THREE TRANSISTOR SRAM
App. No. 10/418,559
→
HIGH DENSITY MEMORY WITH STORAGE CAPACITOR
App. No. 10/403,433
→
METHOD AND APPARATUS FOR PERFORMING ADDRESSING OPERATIONS IN A SUPERSCALAR, SUPERPIPELINED PROCESSOR
App. No. 10/401,170
→
FORWARD ERROR CORRECTOR
App. No. 10/382,400
→
HIGH SPEED FLIP-FLOP
App. No. 10/379,219
→
CONTENT ADDRESSABLE MEMORY WITH CONFIGURABLE CLASS-BASED STORAGE PARTITION
App. No. 10/364,147
→
SUBRANGING ANALOG TO DIGITAL CONVERTER WITH MULTI-PHASE CLOCK TIMING
App. No. 10/359,201
→
FORWARD ERROR CORRECTION APPARATUS AND METHODS
App. No. 10/358,022
→
AUTOMATIC DELAY MATCHING CIRCUIT FOR DATA SERIALIZER
App. No. 10/357,827
→
METHOD AND APPARATUS FOR SHORTENING READ OPERATIONS IN DESTRUCTIVE READ MEMORIES
App. No. 10/356,443
→
LOW VOLTAGE FLASH EEPROM MEMORY CELL WITH IMPROVED DATA RETENTION
App. No. 10/351,113
→
HIGH SPEED ANALOG TO DIGITAL CONVERTER
App. No. 10/349,073
→
CAM CIRCUIT WITH SEPARATE MEMORY AND LOGIC OPERATING VOLTAGES
App. No. 10/350,991
→
METHOD AND APPARATUS TO CONDITIONALLY PRECHARGE A PARTITIONED READ-ONLY MEMORY WITH SHARED WORDLINES FOR LOW POWER OPERATION
App. No. 10/349,121
→
SYSTEM AND METHOD FOR A STARTUP CIRCUIT FOR A DIFFERENTIAL CMOS AMPLIFIER
App. No. 10/338,918
→
DIGITAL-TO-ANALOGUE CONVERTER USING AN ARRAY OF CURRENT SOURCES
App. No. 10/326,168
→
GENERALIZED CONVOLUTIONAL INTERLEAVER/DEINTERLEAVER
App. No. 10/325,525
→
PAGE OPEN HINT IN TRANSACTIONS
App. No. 10/323,381
→
GRAPHICS DISPLAY SYSTEM WITH UNIFIED MEMORY ARCHITECTURE
App. No. 10/322,059
→
DIGITAL TO ANALOG CONVERTER WITH REDUCED RINGING
App. No. 10/320,016
→
CALL-WAITING TONE DETECTION TECHNIQUE
App. No. 10/320,087
→
EXTENDED RANGE VARIABLE GAIN AMPLIFIER
App. No. 10/319,599
→
OPTICAL FIBRE CONNECTOR
App. No. 10/316,885
→
PROGRAMMABLE DIVIDER WITH BUILT-IN PROGRAMMABLE DELAY CHAIN FOR HIGH-SPEED/LOW POWER APPLICATION
App. No. 10/314,954
→
HIGH-SPEED BANK SELECT MULTIPLEXER LATCH
App. No. 10/313,209
→
VARIABLE TRANSCONDUCTANCE VARIABLE GAIN AMPLIFIER UTILIZING A DEGENERATED DIFFERENTIAL PAIR
App. No. 10/307,293
→
FREQUENCY DIVIDING CIRCUIT
App. No. 10/307,308
→
PROGRAMMABLE WRITE SIGNAL GENERATOR
App. No. 10/302,761
→
METHOD AND APPARATUS TO ENSURE DLL LOCKING AT MINIMUM DELAY
App. No. 10/294,372
→
PHASE DETECTORS IN CARRIER RECOVERY FOR OFFSET QAM AND VSB
App. No. 10/288,833
→
LOW VOLTAGE INPUT CURRENT MIRROR CIRCUIT AND METHOD
App. No. 10/288,418
→
WAVELENGTH SENSITIVE DEVICE FOR WAVELENGTH STABILISATION
App. No. 10/288,326
→
FERAM SIDEWALL DIFFUSION BARRIER ETCH
App. No. 10/282,759
→
SINGLE-ENDED SENSE AMPLIFIER WITH SAMPLE-AND-HOLD REFERENCE
App. No. 10/282,880
→
ESD PROTECTION CIRCUIT FOR LOW AMPLITUDE SIGNALS
App. No. 10/281,811
→
SYSTEM AND METHOD FOR COMPENSATING FOR SUPPLY VOLTAGE INDUCED CLOCK DELAY MISMATCHES
App. No. 10/280,569
→
INTEGRATED CAPACITOR AND FUSE
App. No. 10/280,567
→
CONTENT ADDRESSABLE MEMORY WITH PROGRAMMABLE PRIORITY WEIGHTING AND LOW COST MATCH DETECTION
App. No. 10/274,659
→
VARIABLE RATE MODULATOR
App. No. 10/272,759
→
OPTOELECTRONIC MODULE AND METHOD FOR ITS PRODUCTION
App. No. 10/271,264
→
PHASE DETECTOR HAVING IMPROVED TIMING MARGINS
App. No. 10/268,196
→
SYSTEMS AND METHODS OF MONITORING THIN FILM DEPOSITION
App. No. 10/266,857
→
SRAM PROCESS MONITOR CELL
App. No. 10/261,459
→
METHOD AND APPARATUS FOR ADJUSTING THE RESONANT FREQUENCY OF A THIN FILM RESONATOR
App. No. 10/261,312
→
INPUT CIRCUIT WITH HYSTERESIS
App. No. 10/255,577
→
LOW POWER, CHARGE INJECTION COMPENSATED CHARGE PUMP
App. No. 10/253,274
→
MULTIPLEXING AN ADDITIONAL BIT STREAM WITH A PRIMARY BIT STREAM
App. No. 10/245,854
→
MATCH AND PRIORITY ENCODING LOGIC CIRCUIT
App. No. 10/243,076
→
TRANSMISSION DETECTION FOR A LASER POWER MONITOR AND SYSTEM
App. No. 10/238,576
→
METHOD FOR ALIGNMENT OF OPTICAL COMPONENTS
App. No. 10/236,306
→
SOLDER PAD STRUCTURE FOR LOW TEMPERATURE CO-FIRED CERAMIC PACKAGE AND METHOD FOR MAKING THE SAME
App. No. 10/235,762
→
METHOD FOR HANDLING PERSISTENT RESERVATION REGISTRATIONS IN A STORAGE DEVICE
App. No. 10/231,331
→
FREQUENCY DIVISION/MULTIPLICATION WITH JITTER MINIMIZATION
App. No. 10/227,259
→
HIGH SPEED, LOW POWER COMPARATOR
App. No. 10/226,165
→
COMPACT ANALOG-MULTIPLEXED GLOBAL SENSE AMPLIFIER FOR RAMS
App. No. 10/224,841
→
METHOD OF PATTERNING A FERAM CAPACITOR WITH A SIDEWALL DURING BOTTOM ELECTRODE ETCH
App. No. 10/222,718
→
CIRCUIT FOR LINES WITH MULTIPLE DRIVERS
App. No. 10/218,348
→
STABILIZING ELECTRO-ABSORPTION MODULATORS (EAM'S) PERFORMANCE BY MAINTAINING CONSTANT ABSORPTION WITH THE USE OF INTEGRATED TAP COUPLERS
App. No. 10/218,289
→
MATCHING CALIBRATION FOR DUAL ANALOG-TO-DIGITAL CONVERTERS
App. No. 10/217,051
→
SELF-BIASED AMPLIFIER CIRCUIT AND METHOD FOR SELF-BASING AMPLIFIER CIRCUIT
App. No. 10/215,920
→
METHOD AND APPARATUS FOR HIERARCHICAL CLOCK TREE ANALYSIS
App. No. 10/215,125
→
METHOD AND APPARATUS FOR SYNCHRONOUSLY TRANSFERRING DATA ACROSS MULTIPLE CLOCK DOMAINS
App. No. 10/215,157
→
METHOD AND SYSTEM FOR PRODUCING A DRIVE SIGNAL FOR A CURRENT STEERING AMPLIFIER
App. No. 10/214,091
→
HIGH DENSITY MEMORY WITH STORAGE CAPACITOR
App. No. 10/214,618
→
PLUGGABLE ELECTRICAL TRANSCEIVER MODULE WITH HIGH DENSITY FORM FACTOR
App. No. 10/214,337
→
SIGNAL ENCODING FOR TRANSMISSION OF MULTIPLE DIGITAL SIGNALS OVER SINGLE PHYSICAL MEDIUM
App. No. 10/213,225
→
FILTER CENTRE FREQUENCY TEMPERATURE COMPENSATION BY ADJUSTMENT OF THE OPERATING FREQUENCY OF THE HOST SYSTEM
App. No. 10/210,249
→
LAYOUT TECHNIQUE FOR MATCHED RESISTORS ON AN INTEGRATED CIRCUIT SUBSTRATE
App. No. 10/208,043
→
METHOD AND CIRCUIT FOR TUNING A TRANSCONDUCTANCE AMPLIFIER
App. No. 10/209,335
→
SIGNAL AMPLITUDE COMPARATOR
App. No. 10/207,943
→
MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER HAVING ADAPTIVE DISABLING OF CIRCUIT ELEMENTS
App. No. 10/205,735
→
DIFFERENTIAL LATCH AND APPLICATIONS THEREOF
App. No. 10/201,152
→
ON-CHIP MULTIPLE TAP TRANSFORMER AND INDUCTOR
App. No. 10/200,990
→
APPARATUS AND METHOD FOR REDUCING PHASE NOISE IN OSCILLATOR CIRCUITS
App. No. 10/199,113
→
APPARATUS AND METHOD FOR DELAY MATCHING OF FULL AND DIVIDED CLOCK SIGNALS
App. No. 10/197,843
→
INTEGRATED CIRCUIT PACKAGE EMPLOYING FLIP-CHIP TECHNOLOGY AND METHOD OF ASSEMBLY
App. No. 10/199,441
→
MOSFET ANTI-FUSE STRUCTURE
App. No. 10/197,437
→
OPTICAL TRANSMITTING/RECEIVING MODULE INCLUDING AN INTERNAL OPTICAL WAVEGUIDE
App. No. 10/198,573
→
FURNITURE PIECE FACILITATING WIRELESS LOCAL AREA NETWORK ACCESS
App. No. 10/196,165
→
SEMICONDUCTOR OPTICAL MODULATOR
App. No. 10/197,935
→
METHOD AND SYSTEM FOR SYMBOL BINARIZATION
App. No. 10/191,596
→
OUT OF ORDER ASSOCIATIVE QUEUE IN TWO CLOCK DOMAINS
App. No. 10/191,208
→
METHOD AND APPARATUS FOR PROCESSING OF SATELLITE SIGNALS WITHOUT TIME OF DAY INFORMATION
App. No. 10/190,745
→
ADAPTIVE RADIO TRANSCEIVER WITH LOW NOISE AMPLIFICATION
App. No. 10/192,515
→
ELECTRON BEAM LITHOGRAPHY APPARATUS FOCUSED THROUGH SPHERICAL ABERRATION INTRODUCTION
App. No. 10/188,030
→
STRUCTURE AND METHODS FOR MEASUREMENT OF ARBITRATION PERFORMANCE
App. No. 10/188,880
→
ACCELERATED FATIGUE TESTING
App. No. 10/190,102
→
ON-CHIP COMPRESSION OF CHARGE DISTRIBUTION DATA
App. No. 10/190,370
→
ENHANCEMENT OF CARRIER CONCENTRATION IN AS-CONTAINING CONTACT LAYERS
App. No. 10/186,796
→
TRANSPORTABLE MEMORY APPARATUS AND ASSOCIATED METHODS OF INITIALIZING A COMPUTER SYSTEM HAVING SAME
App. No. 10/187,152
→