System and method for USB controllers
View Patent ↗A USB controller is provided with multiple logic channels that share same physical address and data bus at an interface between the host system and the USB Host Controller; and dataports used by the host system to read and/or write data to the USB Host Controller. Also provided is a data packet format for transferring data, which comprises of an Endpoint Transfer Descriptor (“ETD”) that includes an EndPoint Descriptor and a Transfer Descriptor, wherein the host system programs the parameters of a communication channel for a particular Endpoint. Also included is a technique for partitioning a memory storage device into a first memory buffer and a second memory buffer; wherein the size of the first and second memory buffer may be programmed by the host system and the first and/or second memory buffer may contain more than one USB packet.
1. A system, comprising:
an interface to a host system with control logic used for transferring data between the host system and a Universal Bus System (USB) Host Controller;
a memory storage space for storing a plurality of endpoint and transfer descriptors (ETDs) in an ETD table, where each ETD includes an endpoint descriptor with a field for identifying a type of transfer, and a transfer descriptor for an endpoint linked to the endpoint descriptor for each endpoint, the transfer descriptor identifying data that is moved to and from the endpoint, wherein a processing mode for processing each ETD either in a programmable input and output (“PIO”) mode or a direct memory access (DMA) mode is programmed when the ETD table is setup; and if an ETD is processed in the DMA mode, a DMA channel used for processing the ETD is released after the ETD is processed;
a memory buffer for storing at least one USB data packet associated with a USB transfer;
a link for determining a location in the memory buffer associated with the USB transfer specified by an ETD; and
logic that executes the USB transfer using a USB protocol in a priority order, wherein order specifies an order in which the plurality of ETDs are processed.
2. The system of claim 1 , wherein an ETD from amongst the plurality of ETDs is for an isochronous transfer and the ETD for the isochronous transfer is processed before any other ETD for any other endpoint.
3. The system of claim 1 , wherein an ETD from amongst the plurality of ETDs is for an interrupt transfer and the ETD for the interrupt transfer is processed after a pending ETD for an isochronous transfer has been processed.
4. The system of claim 1 , wherein ETDs for a Control transfer and for a Bulk transfer are given the same priority and are processed after pending ETDs for an isochronous transfer and an interrupt transfer has been processed.
5. The system of claim 1 , wherein the interface includes a DMA channel for enabling the DMA mode to process an ETD, if the DMA mode was specified in the ETD table.
6. A Universal Serial Bus (“USB”) Host Controller for transferring information between a host system and a USB device, comprising:
an Endpoint Transfer Descriptor (ETD) table that is setup by the host system at a memory storage space in the USB Host Controller, wherein the ETD table stores a plurality of ETDs, each ETD including an endpoint descriptor with a field for identifying a type of transfer, and a transfer descriptor for an endpoint linked to the endpoint descriptor for each endpoint, the transfer descriptor identifying data that is moved to and from the endpoint and each ETD is enabled using at least one operational register; and when the plurality of ETDs are setup in the ETD table, a processing mode for each ETD is programmed to process the ETD either in a programmable input and output (“PIO”) mode or a direct memory access (DMA) mode, and if an ETD is processed in the DMA mode, a DMA channel used for processing the ETD is released, after the ETD is processed.
7. The USB Host Controller of claim 6 , wherein the USB Host Controller includes a scheduler that scans the ETD table for executing the plurality of ETDs for an isochronous endpoint, an interrupt endpoint, a control endpoint and a bulk endpoint.
8. The USB Host Controller of claim 6 , wherein an ETD from amongst the plurality of ETDs is for an isochronous transfer and the ETD for the isochronous transfer is processed before any other ETD for any other endpoint.
9. The USB Host Controller of claim 6 , wherein an ETD from amongst the plurality of ETDs is for an interrupt transfer and the ETD for the interrupt transfer is processed after a pending ETD for an isochronous transfer has been processed.
10. The USB Host Controller of claim 6 , wherein ETDs for a Control transfer and for a Bulk transfer are given the same priority and are processed after pending ETDs for an isochronous transfer and an interrupt transfer has been processed.
11. The USB Host Contoller of claim 6 , wherein the interface includes a DMA channel for enabling the DMA mode to process an ETD, if the DMA mode was specified in the ETD table.
12. A method for transferring information between a host system and a Universal Serial Bus (“USB”) device via a USB Host Controller, comprising:
setting up an endpoint and transfer descriptor (ETD) table, wherein the ETD table is set up and loaded into a memory storage space in the USB Host Controller by the host system, and the ETD table stores a plurality of ETDs, which are enabled using at least one operational register; each ETD includes an Endpoint Descriptor with at least a field for identifying a type of transfer, and a Transfer Descriptor for an endpoint linked to the Endpoint Descriptor, the Transfer Descriptor identifying data that is moved to and from the endpoint; and when the plurality of ETDs are setup in the ETD table, a processing mode for processing each of the plurality of ETDs either in a programmable input and output (“PIO”) mode or a direct memory access (DMA) mode is programmed;
scanning the plurality of ETDs at a start of frame, wherein the Host Controller scans the plurality of ETDs; and
executing the plurality of ETDs based on a priority order; wherein the priority order specifies an order in which the ETDs are processed and if an ETD is processed in the DMA mode, a DMA channel used for processing the ETD is released after the ETD is processed.
13. The method of claim 12 , further comprising:
reserving a percentage of time in a frame for executing control transfers and bulk transfers as specified by ETDs associated with control transfers and bulk transfers.
14. The method of claim 12 , wherein an ETD from amongst the plurality of ETDs is for an isochronous transfer and the ETD for the isochronous transfer is processed before any other ETD for any other endpoint.
15. The method of claim 12 , wherein an ETD from amongst the plurality of ETDs is for an interrupt transfer and the ETD for the interrupt transfer is processed after a pending ETD for an isochronous transfer has been processed.
16. The method of claim 12 , wherein ETDs for a Control transfer and for a Bulk transfer are given the same priority and are processed after pending ETDs for an isochronous transfer and an interrupt transfer has been processed.