Granted Patent B2

US 8,327,042 · App. 12/875,500 · Granted Dec 4, 2012

Abstract

Claims (40)

1. A method for configuring a plurality of input/output (I/O) interconnect switch ports, the method comprising:

starting a link training and status state machine (LTSSM) for each of the plurality of ports;

placing each of the LTSSMs in a receiver detect state;

changing all of the LTSSMs to a polling state only once receivers are detected or timeouts occur in the receiver detect states in each of the LTSSMs;

changing all of the LTSSMs to a configuration state only once polling is successful or timeouts occur in the polling states in each of the LTSSMs; and

completing the configuration state of each of the LTSSMs.

2. The method of claim 1 , wherein the LTSSMs can progress from the configuration state to other states without regard for others of the plurality of LTSSMs.

3. The method of claim 1 , wherein the starting includes:

obtaining a count of available LTSSMs on the I/O interconnect switch;

if the count of available LTSSMs is less than the number of the plurality of ports, then only starting a number of LTSSMs equal to the count.

4. The method of claim 1 , wherein the polling state is a polling configuration state.

5. A method for configuring a plurality of links on a switch, the method comprising:

sending a link request for each of the plurality of links, wherein the link requests each include information regarding a number of lanes requested for the corresponding link;

detecting that a plurality of link requests have been successful; and

starting a plurality of LTSSMs in parallel, wherein each of the LTSSMs corresponds to a different successful link request, wherein each of the LTSSMs comprise a plurality of states, wherein for at least one of the states, progression to a successive state is delayed until the same state is completed for all the LTSSMs.

6. The method of claim 5 , wherein a state is completed if actions taken during the state are successful or if a timeout period is reached.

7. The method of claim 5 , wherein the switch is a Gigabit Ethernet switch.

8. The method of claim 5 , wherein the at least one of the states includes a receiver detect state.

9. The method of claim 8 , wherein the at least one of the states also includes a polling state.

10. A switch comprising:

a plurality of ports;

a plurality of LTSSMs;

a processor configured to:

start an LTSSM for each link to establish on the plurality of ports;

place each of the started LTSSMs in a receiver detect state;

advance all of the started LTSSMs to a polling state once the receiver detect states for all of the LTSSMs have completed; and

advance all of the started LTSSMs to a configuration state once the polling states for all of the LTSSMs have completed.

11. The switch of claim 10 , wherein the switch is a Gigabit Ethernet switch.

12. The switch of claim 10 , wherein the switch is an I/O interconnect switch.

13. The switch of claim 10 , wherein a receiver detect state has completed once a receiver is detected or a timeout is reached.

14. The switch of claim 10 , wherein a polling state has completed once a polling success message is received or a timeout is reached.

15. A non-transitory computer readable medium for storing in non-transitory tangible form computer instructions executable by a processor for configuring a plurality of ports in a switch, the method comprising:

starting a link training and status state machine (LTSSM) for each of the plurality of ports;

placing each of the LTSSMs in a receiver detect state;

changing all of the LTSSMs to a polling state only once receivers are detected or timeouts occur in the receiver detect states in each of the LTSSMs;

changing all of the LTSSMs to a configuration state only once polling is successful or timeouts occur in the polling states in each of the LTSSMs; and

completing the configuration state of each of the LTSSMs.

16. The non-transitory computer readable medium of claim 15 , wherein when the configuration state of a particular LTSSM is completed, the particular LTSSM advances to a subsequent state without regard for the other of the LTSSMs.

17. The non-transitory computer readable medium of claim 15 , wherein the switch is a switch configured in accordance with the PCI Express standard.

18. The non-transitory computer readable medium of claim 15 , wherein the processor is further configured to detect completion of a link request message for one of the plurality of ports prior to starting a LTSSMs for the one of the plurality of ports.

Assignments (8)