IP Library Granted Patent US 9,141,571
Granted Patent B2
US 9,141,571 · App. 13/624,781 · Granted Sep 22, 2015

PCI express switch with logical device capability

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Quick Facts
Patent No.
US 9,141,571
App. No.
13/624,781
Granted
Sep 22, 2015
Kind
B2
Abstract

A PCIe switch implements a logical device for use by connected host systems. The logical device is created by logical device enabling software running on a host management system. The logical device is able to consolidate one or more physical devices or may be entirely software-based. Commands from the connected host are processed in the command and response queues in the host and are also reflected in shadow queues stored in the management system. A DMA engine associated with the connected host is set up to automatically trigger on queues in the connected (local) host. Commands are sent to the physical devices to complete the work and a completion signal is sent to the management software and a response to the work is sent directly to the connected host, which is not aware that the logical device is non-existent and is implemented by software in the management system.

Claims (64)

1. A method of enabling operation of a synthetic device in a PCIe switch, the method comprising:

presenting the synthetic device to a local host component connected to the switch;

capturing read and write operations within the local host, thereby enabling a management system of the switch to create a shadow copy of local host component queues;

notifying the management system of local host driver operations, wherein the local host loads a driver;

enabling writes that occur in the local host to be reflected in a memory on the management system;

enabling creation of shadow queues on the management system, said shadow queues reflecting command and response queues in the local host;

setting up a DMA engine associated with the local host port to automatically trigger on the queues in the local host;

enabling mapping of synthetic device doorbells to DMA engine doorbells; and

mapping addresses between the local host and the management system thereby enabling data transmission between the local host and a physical device associated with the synthetic device.

2. A method as recited in claim 1 further comprising:

sending interrupt vectors on the local host to the management system.

3. A method as recited in claim 1 further comprising:

associating interrupt vectors with DMA engine queues for appropriate host device response.

4. A method as recited in claim 1 wherein a plurality of local hosts and a plurality of physical devices use the synthetic device.

5. A method as recited in claim 1 wherein the management system has a synthetic device enablement module that provides executable instructions for implementing the synthetic device in the switch.

6. A method as recited in claim 1 wherein the management system has a shadow copy of the queues stored on the local host.

7. A method as recited in claim 1 wherein, when the physical device completes a function requested by the local host, a completion signal is sent to the management system and a response is sent directly to the local host.

8. A method as recited in claim 5 wherein the enablement module performs operations on data from the local host and directs the data to the physical device.

9. A method as recited in claim 1 wherein there is a control path between the management system and the physical device for transmitting commands relating to the synthetic device and a data path between the physical device and the local host.

10. A method as recited in claim 1 wherein there is a one-to-one mapping of updates to the queues in the local host that are reflected in the shadow queues in the management system.

11. A method as recited in claim 1 wherein the synthetic device is a software-created device without an associated physical device.

12. A method as recited in claim 1 further comprising

allocating the queues in the local host and writing the queues to the synthetic device.

13. A PCI express switch in connection with a management system having a logical device enabler module for implementing a logical consolidation of physical devices in the switch,

wherein the logical device enabler module presents the logical consolidation of physical devices to a connected host as a synthetic device,

wherein the synthetic device is used by the connected host to write data to and read date from the physical devices, and

wherein a memory in the management system that:

stores shadow copies of a command queue, a response queue, and a doorbell as stored in the connected host;

enables mapping of synthetic device doorbells to DMA engine doorbells of a DMA engine of the connected host; and

enables mapping of addresses between the connected host and the management system to enable data transmission between the physical devices and the connected host.

14. A method of enabling operation of a synthetic device in a PCIe switch, the method comprising:

presenting the synthetic device to a local host component connected to the switch;

capturing read and write operations within the local host, thereby enabling a management system of the switch to create a shadow copy of local host component queues;

notifying the management system of local host driver operations, wherein the local host loads a driver;

enabling writes that occur in the local host to be reflected in a memory on the management system;

enabling creation of shadow queues on the management system, said shadow queues reflecting command and response queues in the local host;

setting up a DMA engine associated with the local host port to automatically trigger on the queues in the local host; and

enabling mapping of synthetic device doorbells to DMA engine doorbells; and

allocating the queues in the local host and writing the queues to the synthetic device.

15. A method as recited in claim 14 further comprising:

sending interrupt vectors on the local host to the management system; and

associating the interrupt vectors with DMA engine queues for appropriate host device response.

16. A method as recited in claim 14 wherein

wherein the management system has a synthetic device enablement module that provides executable instructions for implementing the synthetic device in the switch and the enablement module performs operations on data from the local host and directs the data to the physical device.

17. A method as recited in claim 14 wherein there is a control path between the management system and the physical device for transmitting commands relating to the synthetic device and a data path between the physical device and the local host.

18. A method as recited in claim 14 wherein there is a one-to-one mapping of updates to queues in the local host that are reflected in the shadow queues in the management system.

19. A method as recited in claim 14 further comprising mapping addresses between the local host and the management system thereby enabling data transmission between the local host and a physical device associated with the synthetic device.

20. A method of enabling operation of a synthetic device in a PCIe switch, the method comprising:

presenting the synthetic device to a local host component connected to the switch;

capturing read and write operations within the local host, thereby enabling a management system of the switch to create a shadow copy of local host component queues;

notifying the management system of local host driver operations, wherein the local host loads a driver;

enabling writes that occur in the local host to be reflected in a memory on the management system;

enabling creation of shadow queues on the management system, said shadow queues reflecting command and response queues in the local host;

setting up a DMA engine associated with the local host port to automatically trigger on queues in the local host; and

enabling mapping of synthetic device doorbells to DMA engine doorbells,

wherein the synthetic device is a software-created device without an associated physical device.

21. A PCI express switch, comprising

a management system operable to logically consolidate a plurality of physical devices into a synthetic device, to present the synthetic device to a host, and to allocate queues in the host for writing to the physical devices; and

a memory operable to store shadow copies of the queues in the host,

wherein the management system is further operable to map the queues in the host to the shadow copies of the queues in the memory, and to direct the host to DMA data from the host queues to the shadow copies of the queues to write data to the physical devices via the synthetic device.

22. The PCI express switch of claim 21 , wherein:

the synthetic device is operable to DMA data from the shadow copies of the queues in the memory to the host queues in response to a read operation by the host.

23. The PCI express switch of claim 22 , wherein:

the synthetic device is software executed operate on the data from the host to direct the data to the physical device.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 034069-0494) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: PLX TECHNOLOGY, INC.
Reel/Frame 037682/0802 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2015
From: PLX TECHNOLOGY, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035615/0767 →
PATENT SECURITY AGREEMENT Recorded Oct 28, 2014
From: PLX TECHNOLOGY, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 034069/0494 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2012
From: SUBRAMANIYAN, NAGARAJAN; REGULA, JACK; DODSON, JEFFREY MICHAEL
To: PLX TECHNOLOGY, INC.
Reel/Frame 029314/0340 →