Switch with synthetic device capability
View Patent ↗A method of sharing of a function of a device with a plurality of hosts through a PCIe switch is provided. A function on a device is presented to a first host and a second host through the switch. Read and write on the function's register set within the first host and within the second host are captured, thereby enabling a management system of the switch to create a shadow copy of the first host register sets and second host register sets. The creation of sets of shadow queues on the management system is enabled. The first set of shadow queues of the first set of registers is used to direct read and write operations from the first host to the function. The second set of shadow queues of the second set of registers is used to direct read and write operations from the second host to the function.
1. A method of sharing of a function of a device with a plurality of hosts through a PCIe switch, the method comprising:
presenting a function on a device to a first host of a plurality of hosts and a second host of the plurality of hosts through the switch;
capturing read and write on the function's register set within the first host and within the second host, thereby enabling a management system of the switch to create a shadow copy of first host register sets and second host register sets;
enabling creation of sets of shadow queues on the management system, wherein a first set of shadow queues is a first set of registers for read and write operations between the function and the first host and wherein a second set of shadow queues is a second set of registers for read and write operations between the function and the second host, said sets of shadow queues reflecting command and response queues in the first and second hosts;
assigning, by the management system, for the function a first address for the first host and a second address for the second host, wherein the first address has a first prefix associated with the first host and the second address has a second prefix associated with the second host;
intercepting a PCIe transaction from the function of the device for one of the first and second hosts; and
translating a prefixed address to route the PCIe transaction to the appropriate host and to use the first set of shadow queues of the first set of registers to direct read and write operations from the first host to the function and use the second set of shadow queues of the second set of registers to direct read and write operations from the second host to the function based on the PCIe transaction.
2. A method as recited in claim 1 , wherein the device is an NVMe device.
3. The method, as recited in claim 1 , wherein the enabling creation of sets of shadow queues on the management system comprises setting up a DMA operation.
4. The method, as recited in claim 3 , wherein on completion of a device command the device writes a completion entry into a completion queue in the management system or directly to the first host or second host.
5. The method, as recited in claim 4 , wherein interrupts on completion queues are forwarded to the first host or the second host through the management system or are directly sent to the first host or the second host.
6. The method, as recited in claim 1 , further comprising assigning, by the management system, for the first function a first address for the first host and a second address for the second host.
7. The method, as recited in claim 6 , wherein the first address is a host address with a first prefix and the second address is the host address with a second prefix different from the first prefix.
8. The method, as recited in claim 1 , wherein the enabling creation of sets of shadow queues on the management system comprises setting up a DMA operation.
9. The method, as recited in claim 1 , wherein on completion of a device command the device writes a completion entry into a completion queue in the management system or directly to the first host or second host.
10. The method, as recited in claim 1 , wherein interrupts on completion queues are forwarded to the first host or the second host through the management system or are directly sent to the first host or the second host.
11. A Peripheral Component Interface Express (PCIe) switch interfacing between a plurality of hosts and a plurality of devices, the PCIe switch comprising:
a virtual function operable to interface with the devices through Single Root Input/Output Virtualization (SR-IOV); and
a management system operable to detect addresses of registers of each of the hosts, to prefix those addresses, to establish shadow copies of registers of the hosts in the PCIe switch based on the prefixed addresses, to detect a command from a first of the devices for a first of the hosts via the virtual function in response to an Input/Output (I/O) request of the first host system, to retain packets associated with the command in the shadow copy of the first host register, to remove the prefixed address from the command, and to forward the packets to the first host without conflicting with addresses of the remaining hosts.
12. A method operable in a Peripheral Component Interface Express (PCIe) switch interfacing between a plurality of hosts and a plurality of devices, the method comprising:
interfacing a virtual function with the devices through Single Root Input/Output Virtualization (SR-IOV);
detecting addresses of registers of each of the hosts;
prefixing those addresses;
establishing shadow copies of registers of the hosts in the PCIe switch based on the prefixed addresses;
detecting a command from a first of the devices for a first of the hosts via the virtual function in response to an Input/Output (I/O) request of the first host system;
retaining packets associated with the command in the shadow copy of the first host register;
removing the prefixed address from the command; and
forwarding the packets to the first host without conflicting with addresses of the remaining hosts.