IP Library Granted Patent US 6,851,009
Granted Patent B1
US 6,851,009 · App. 10/446,402 · Granted Feb 1, 2005

Method, system and apparatus for a computer subsystem interconnection using a chain of bus repeaters

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,851,009
App. No.
10/446,402
Granted
Feb 1, 2005
Kind
B1
Abstract

The invention discloses methods and apparatus for broadcasting information across an interconnect that includes a plurality of nodes each connected to its adjacent node(s) using one or more links. The nodes can emit cells containing transaction sub-actions onto the links. As a node receives a cell the node retransmits the cell onto other links as the cell is being received. Thus, reducing the latency imposed by the node. The node also captures the transaction sub-action while it the cell is retransmitted. The node responds to the transaction sub-action by manipulating shared handshake lines that are bussed with the other nodes. The invention enables snooping cache protocols to be successfully used in a larger multi-processor computer system than the prior art.

Claims (22)

1. A method for broadcasting information among interconnected nodes, including the steps of:

receiving a packet at a first node from a second node, the packet containing at least a transaction sub-action;

retransmitting the packet from the first node, wherein retransmitting of the packet is performed at least in part while as the packet is being received by the first node; and

capturing the sub-action at the first node as the packet is being retransmitted; and

maniplulating handshake lines between the first node and at least one other node in response to the sub-action.

2. A method as in claim 1 , wherein the sub-action is a memory read request.

3. A method as in claim 1 , wherein the sub-action is a memory read response.

4. A method as in claim 1 , wherein the sub-action is an invalidation.

5. A method as in claim 1 , wherein the step of manipulating handshake lines further comprises setting each of the handshake lines with a tag value.

6. A method as in claim 5 , wherein the tag value for each of the handshake lines is associated with a buffer in the first node.

7. A method as in claim 1 , wherein each of the handshake lines includes a HIT* tag line and a DONE tag line.

8. A node interconnected to other nodes, comprising:

an interface to a link to a second node across which said node receives a packet containing at least a transaction sub-action;

a repeater that retransmits the packet from the node while at least a portion of the packet is being received at the interface;

an interface to handshake lines between the node and the other nodes; and

a memory and cache agent that captures the sub-action as the packet is being retransmitted and that manipulates that handshake lines in response to the sub-action.

9. A node as in claim 8 , wherein the sub-action is a memory read request.

10. A node as in claim 8 , wherein the sub-action is a memory read response.

11. A node as in claim 8 , wherein the sub-action is an invalidation.

12. A node as in claim 8 , wherein the cache agent manipulates the handshake lines by setting each of the handshake lines with a tag value.

13. A node as in claim 12 , wherein the memory of the memory and cache agent includes plural buffers, and wherein the tag values for the handshake lines are associated with the plural buffers.

14. A node as in claim 8 , wherein each of the handshake lines includes a HIT* tag line and a DONE tag line.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 034069-0494) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: PLX TECHNOLOGY, INC.
Reel/Frame 037682/0802 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2015
From: PLX TECHNOLOGY, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035615/0767 →
PATENT SECURITY AGREEMENT Recorded Oct 28, 2014
From: PLX TECHNOLOGY, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 034069/0494 →