IP Library Granted Patent US 7,996,802
Granted Patent B2
US 7,996,802 · App. 12/230,387 · Granted Aug 9, 2011

Method of verifying circuit and computer-readable storage medium for storing computer program

Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 7,996,802
App. No.
12/230,387
Granted
Aug 9, 2011
Kind
B2
Abstract

A method of verifying a circuit for use in an apparatus for verifying a circuit operation indicated by circuit information, the circuit including a plurality of logic circuits and at least one connection line between the logic circuits, the method includes: obtaining information of a plurality of pieces of asynchronous circuits from the circuit information; determining information of asynchronous circuits of a first type and a second type stored in a library; extracting information of an asynchronous circuit of a third type including the asynchronous circuits of the first type and the second type; and extracting verification information associated with the information of the asynchronous circuit of the third type, for verifying the circuit.

Claims (24)

1. A method of verifying a circuit for use in an apparatus for verifying a circuit operation indicated by circuit information, the circuit comprising a plurality of logic circuits and at least one connection line between the logic circuits, the method comprising:

obtaining information of a plurality of asynchronous circuits each comprising a plurality of registers connected with an connection line, the registers being driven by different clocks, from the circuit information;

determining information of at least one asynchronous circuit of a first type stored in a library storing information of a plurality of types of asynchronous circuits having different circuit configurations respectively, out of the circuit information;

determining information of at least one asynchronous circuit of a second type stored in the library out of the circuit information;

extracting information of an asynchronous circuit of a third type including an asynchronous circuit of the first type and an asynchronous circuit of the second type; and

extracting verification information associated with the information of the asynchronous circuit of the third type, for verifying the circuit.

2. The method of claim 1 , wherein the information of the asynchronous circuit of the third type is extracted when the asynchronous circuit of the first type and the asynchronous circuit of the second type are combined so as to generate a new asynchronous circuit.

3. The method of claim 1 , wherein the information of the asynchronous circuit of the first type is verified by verification information for a circuit operation indicated by the asynchronous circuit of the first type, and the information of the asynchronous circuit of the second type is verified by verification information for a circuit operation indicated by the asynchronous circuit of the second type.

4. The method of claim 1 , wherein the verification information associated with the information of the asynchronous circuit of the third type includes information of at least one combinational circuit connected between the registers, the combinational circuit comprising no registers.

5. The method of claim 1 , wherein the verification information associated with the information of the asynchronous circuit of the third type includes assertion information for verifying the asynchronous circuit logically operates in accordance with expected values.

6. The method of claim 1 , wherein the verification information of the third type includes coverage information indicating a relationship between the asynchronous circuits.

7. The method of claim 1 , wherein the verification information of the third type includes information of style check result on basis of at least one style check item included in the library, the style check item including style requirements of the asynchronous circuit.

8. A non-transitory computer-readable storage medium storing a computer program of verifying a circuit for use in an apparatus for verifying a circuit operation indicated by circuit information, the circuit comprising a plurality of logic circuits and at least one connection line between the logic circuits, the computer program comprising instructions for:

obtaining information of a plurality of pieces of asynchronous circuits each comprising a plurality of registers connected with an connection line, the registers being driven by different clocks, from the circuit information;

determining information of at least one asynchronous circuit of a first type stored in a library storing information of a plurality of types of asynchronous circuits having different circuit configurations respectively, out of the circuit information;

determining information of at least one asynchronous circuit of a second type stored in the library out of the circuit information;

extracting information of an asynchronous circuit of a third type including an asynchronous circuit of the first type and an asynchronous circuit of the second type; and

extracting verification information associated with the information of the asynchronous circuit of the third type, for verifying the circuit.

9. The non-transitory computer-readable storage medium of claim 8 , wherein the information of the asynchronous circuit of the third type is extracted when the asynchronous circuit of the first type and the asynchronous circuit of the second type are combined so as to generate a new asynchronous circuit.

10. The non-transitory computer-readable storage medium of claim 8 , wherein the information of the asynchronous circuit of the first type is verified by verification information for a circuit operation indicated by the asynchronous circuit of the first type, and the information of the asynchronous circuit of the second type is verified by verification information for a circuit operation indicated by the asynchronous circuit of the first type.

11. The non-transitory computer-readable storage medium of claim 8 , wherein the verification information associated with the information of the asynchronous circuit of the third type includes information of at least one combinational circuit connected between the registers, the combinational circuit without comprising any registers.

12. The non-transitory computer-readable storage medium of claim 8 , wherein the verification information associated with the information of the asynchronous circuit of the third type includes assertion information for verifying the asynchronous circuit logically operates in accordance with expected values.

13. The non-transitory computer-readable storage medium of claim 8 , wherein the verification information of the third type includes coverage information indicating a relationship between asynchronous circuits.

14. The non-transitory computer-readable storage medium of claim 8 , wherein the verification information of the third type includes information of style check result on basis of at least one style check item included in the library, the style check item including style requirements of the asynchronous circuit.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0637 →
CHANGE OF NAME Recorded Jul 27, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024794/0500 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2008
From: IKEDA, NORIYUKI; MATSUURA, TAKASHI
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021516/0718 →
Priority Claims (1)
JP 2007-224750 · Aug 30, 2007 · national
Continuity (1)
Related Publication 20090064065A1 · Mar 5, 2009