Semiconductor circuit
In a conventional circuit to buffer differential clock signals at plural stages, the deteriorations of duty ratios caused by the variations of transistors constituting the circuit have not been compensated. Further, when it is attempted to increase the effect of compensating the duty ratios, the size of the circuit increases and the consumed electric current also increases accordingly. A semiconductor circuit according to the present invention includes: a differential input section to receive input differential signals; differential signal output terminals to output output differential signals in accordance with the voltages input into the differential input section; a low-pass filter to extract the DC components of signals output from the differential signal output terminals; and a load resistor section connected to the differential input section, wherein resistance values are determined on the basis of the DC components of the signals extracted with the low-pass filter.
1 . A semiconductor circuit comprising:
a differential input section to receive input differential signals;
differential signal output terminals to output output differential signals in accordance with the voltages input into said differential input section;
a low-pass filter to extract the DC components of signals output from said differential signal output terminals; and
a load resistor section connected to said differential input section, wherein resistance values are determined on the basis of the DC components of the signals extracted with said low-pass filter.
2 . The semiconductor circuit according to claim 1 , wherein cross-coupled CMOS inverters are connected to said differential signal output terminals.
3 . The semiconductor circuit according to claim 1 , wherein buffers are connected in plural stages between said differential signal output terminals and said low-pass filter.
4 . The semiconductor circuit according to claim 1 , wherein said load resistor section is connected in series with said differential input section.
5 . The semiconductor circuit according to claim 1 , wherein said load resistor section is connected in parallel with said differential input section.
6 . The semiconductor circuit according to claim 1 , wherein said differential input section includes CMOS inverters.
7 . The semiconductor circuit according to claim 1 ,
wherein said differential input section has first transistors and second transistors; and
wherein said differential signal output terminals are placed between said first transistors and said second transistors, respectively.
8 . The semiconductor circuit according to claim 7 ,
wherein said load resistor section includes third transistors and fourth transistors;
wherein said third transistors are connected between ground terminals and said first transistors, respectively; and
wherein said fourth transistors are connected between power supply voltage terminals and said second transistors, respectively.
9 . The semiconductor circuit according to claim 7 ,
wherein said load resistor section includes third transistors; and
wherein said third transistors are connected between ground terminals and said first transistors, respectively.
10 . The semiconductor circuit according to claim 7 ,
wherein said load resistor section includes fourth transistors; and
wherein said fourth transistors are connected between power supply voltage terminals and said second transistors, respectively.
11 . The semiconductor circuit according to claim 7 ,
wherein said load resistor section includes third transistors and fourth transistors;
wherein said fourth transistors are connected between power supply voltage terminals and said differential signal output terminals, respectively; and
wherein said third transistors are connected between ground terminals and said differential signal output terminals, respectively.
12 . The semiconductor circuit according to claim 7 ,
wherein said load resistor section includes third transistors; and
wherein said third transistors are connected between ground terminals and said differential signal output terminals, respectively.
13 . The semiconductor circuit according to claim 7 ,
wherein said load resistor section includes fourth transistors; and
wherein said fourth transistors are connected between power supply voltage terminals and said differential signal output terminals, respectively.
14 . The semiconductor circuit according to claim 1 , wherein said low-pass filter has a resistor section and a capacitor section.
15 . The semiconductor circuit according to claim 14 , wherein said resistor section includes transfer gates.
16 . The semiconductor circuit according to claim 14 , wherein said resistor section includes resistive elements.
17 . The semiconductor circuit according to claim 14 , wherein said capacitor section includes the gate capacitors of transistors.
18 . The semiconductor circuit according to claim 14 ,
wherein said resistor section includes a first transfer gate and a second transfer gate;
wherein said capacitor section includes the gate capacitor of a fifth transistor and the gate capacitor of a sixth transistor;
wherein one of the differential signals output from said differential signal output terminals is input into one of the terminals of said first transfer gate and the other terminal is connected to a first node;
wherein the drain and the source of said fifth transistor are connected to said first node and the gate thereof is connected to a second node;
wherein the other of the differential signals output from said differential signal output terminals is input into one of the terminals of said second transfer gate and the other terminal is connected to the second node; and
wherein the drain and the source of said sixth transistor are connected to said second node and the gate thereof is connected to the first node.
19 . The semiconductor circuit according to claim 14 ,
wherein said resistor section includes a first transfer gate and a second transfer gate;
wherein said capacitor section includes the gate capacitor of a fifth transistor and the gate capacitor of a sixth transistor;
wherein one of the differential signals output from said differential signal output terminals is input into one of the terminals of said first transfer gate and the other terminal is connected to a first node;
wherein the drain and the source of said fifth transistor are connected to a ground terminal and the gate thereof is connected to the first node;
wherein the other of the differential signals output from said differential signal output terminals is input into one of the terminals of said second transfer gate and the other terminal is connected to a second node; and
wherein the drain and the source of said sixth transistor are connected to the ground terminal and the gate thereof is connected to the second node.
20 . The semiconductor circuit according to claim 1 , wherein capacitors are connected to said differential signal output terminals.