IP Library Granted Patent US 8,312,432
Granted Patent B2
US 8,312,432 · App. 12/232,005 · Granted Nov 13, 2012

Method of adjusting timing difference between pre-corrected source program and post-corrected source program, compiler and information processor

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Quick Facts
Patent No.
US 8,312,432
App. No.
12/232,005
Granted
Nov 13, 2012
Kind
B2
Abstract

A method of adjusting a control timing accompanying a program correction of a machine language program executed by an information processor includes preparing a first machine language program obtained by compiling a first source program and generating a second intermediate language program from a second source program, the second source program being corrected from the first source program. Then, the method computes a first number of clock cycles, that is a number of clock cycles to execute a first machine language program obtained by compiling the first source program and computes a second number of clock cycles, that is a number of clock cycles to execute a second machine language program obtained by compiling the second source program, using the second intermediate language program, the second intermediate language program including an instruction that is uniquely correlated with a machine language instruction of the second machine language program.

Claims (13)

1. A method of adjusting a control timing accompanying a program correction of a machine language program executed by an information processor, comprising:

preparing a first machine language program obtained by compiling a first source program;

generating a second intermediate language program from a second source program, the second source program being corrected from the first source program;

computing a first number of clock cycles, that is a number of clock cycles to execute the first machine language program;

computing a second number of clock cycles, that is a number of clock cycles to execute a second machine language program obtained by compiling the second source program, using the second intermediate language program, the second intermediate language program including an instruction that is uniquely correlated with a machine language instruction of the second machine language program;

comparing the second number of clock cycles with the first number of clock cycles; and

adjusting the second machine language program by performing at least one of addition, deletion and modification of the second machine language program to reduce a difference between the first number of clock cycles and second number of clock cycles, based on the second intermediate language program.

2. The method according to claim 1 , wherein the second number of clock cycles is computed using a first intermediate language program generated from the first source program, and the first intermediate language program includes an instruction that is uniquely correlated with the machine language instruction of the first machine language program.

3. The method according to claim 2 , wherein the comparison of the first number of clock cycles and second number of clock cycles is performed for each instruction of the first intermediate language program and the second intermediate language program, or for each instruction set which is a group of plural instructions thereof.

4. The method according to claim 1 , wherein the machine language instruction contains an information specifying the number of clock cycles used to control the number of clock cycles of the corresponding machine language instruction in the information processor.

5. The method according to claim 4 , wherein the information processor determines a number of clock cycles which should execute the machine language instruction from the information specifying the number of clock cycles, and executes the machine language instruction based on the determined number of clock cycles.

6. The method according to claim 5 ,

wherein the information specifying the number of clock cycles comprises an information showing an increase or decrease of the number of clock cycles of the machine language instruction; and wherein the information processor reflects the information specifying the number of clock cycles in the number of clock cycles of the machine language instruction.

Assignments (2)
CHANGE OF NAME Recorded Oct 28, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025214/0687 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2008
From: MORI, KENJI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 021566/0967 →