Latch circuit
A latch circuit includes: a first terminal; a second terminal; a first data-gating circuit coupled to the first terminal and the second terminal, the first data-gating circuit non-reversely gating the second signal in response to the first signal to reveal a third signal; a second data-gating circuit coupled to the first terminal and the second terminal, the second data-gating circuit reversely gating the second signal in response to the first signal to reveal a fourth signal; a third terminal receiving a fifth signal; a selector circuit coupled to the first data-gating circuit and the second data-gating circuit, the selector circuit outputting one of the third signal and the fourth signal in response to the fifth signal to latch one of the third signal and the fourth signal, respectively; and a bistable circuit coupled to the selector circuit, the bistable circuit holding one of the third signal and the fourth signal.
1 . A latch circuit comprising:
a first terminal receiving a first signal;
a second terminal receiving a second signal;
a first data-gating circuit coupled to the first terminal and the second terminal, said first data-gating circuit non-reversely gating the second signal in response to the first signal to reveal a third signal;
a second data-gating circuit coupled to the first terminal and the second terminal, said second data-gating circuit reversely gating the second signal in response to the first signal to reveal a fourth signal;
a third terminal receiving a fifth signal;
a selector circuit coupled to the first data-gating circuit and the second data-gating circuit, said selector circuit outputting one of the third signal and the fourth signal in response to the fifth signal to latch one of the third signal and the fourth signal, respectively; and
a bistable circuit coupled to the selector circuit, said bistable circuit holding one of the third signal and the fourth signal.
2 . A latch circuit comprising:
a first data-gating circuit non-reversely switching in response to a first signal;
a second data-gating circuit non-reversely switching in response to a second signal;
a first circuit including said first data-gating circuit and said second data-gating circuit coupled together in series;
a third data-gating circuit reversely switching in response to the first signal;
a fourth data-gating circuit reversely switching in response to the second signal;
a second circuit including said third data-gating circuit and said fourth data-gating circuit coupled together in series;
a first terminal receiving a third signal;
a second terminal revealing a fourth signal;
a third circuit including one circuit, the one circuit including said first circuit and said second circuit coupled together in parallel, the one circuit having one terminal being coupled to said first terminal and another terminal being coupled to said second terminal; and
a bistable circuit coupled to said second terminal, said bistable circuit holding the fourth signal.
3 . The latch circuit according to claim 2 ,
wherein said bistable circuit comprises:
a first inverter having a first input terminal to receive a first input signal, and a first output terminal to reveal a first inverting signal for the first input signal, said first output terminal of said first inverter being coupled to said second terminal; and
a second inverter having a second input terminal to receive a second input signal, and a second output terminal to reveal a second inverting signal for the second input signal, said second input terminal of said second inverter being coupled to said second terminal, said second output terminal of said second inverter being coupled to said first input terminal of said first inverter.
4 . A latch circuit comprising:
a first transistor being of a first conduction type and switching in response to a first signal;
a second transistor being of said first conduction type and switching in response to a second signal;
a first circuit including said first transistor and said second transistor coupled together in series;
a third transistor being of a second conduction type different from said first conduction type and switching in response to the first signal;
a fourth transistor being of said second conduction type and switching in response to the second signal;
a second circuit including said third transistor and said fourth transistor coupled together in series;
a first terminal receiving a third signal;
a second terminal revealing a fourth signal;
a third circuit including one circuit, the one circuit including said first circuit and said second circuit coupled together in parallel, the one circuit having one terminal being coupled to said first terminal and another terminal being coupled to said second terminal; and
a bistable circuit coupled to said second terminal, said bistable circuit holding the fourth signal.
5 . The latch circuit according to claim 4 ,
wherein said bistable circuit comprises:
a first inverter having a first input terminal to receive a first input signal, and a first output terminal to reveal a first inverting signal for the first input signal, said first output terminal of said first inverter being coupled to said second terminal; and
a second inverter having a second input terminal to receive a second input signal, and a second output terminal to reveal a second inverting signal for the second input signal, said second input terminal of said second inverter being coupled to said second terminal, said second output terminal of said second inverter being coupled to said first input terminal of said first inverter.