Semiconductor integrated circuit

1. A semiconductor integrated circuit comprising:

a macro capable of transitioning to a predetermined state;

a first register coupled to said macro to receive a predetermined signal to store a first value indicating whether or not said macro is in said predetermined state at a specific time point, and to store a second value indicating whether or not the macro is in the predetermined state at another specific time point which is after said specific time point; and

a second register configured to store said first value based on the predetermined signal of said specific time point as a value indicating whether or not said macro has been in said predetermined state before said specific time point whereas the second register retains said stored first value and does not update said first value to said second value based on the predetermined signal of said another specific time point.

2. The semiconductor integrated circuit according to claim 1 , wherein said predetermined state comprises a reset state, and said macro transitions to said reset state in response to receiving a reset signal.

3. The semiconductor integrated circuit according to claim 1 , wherein said first register stores said first and second values, respectively, when said macro is debugged.

4. The semiconductor integrated circuit according to claim 1 , further comprising a control circuit that outputs said first value from said first and second registers to an external device and outputs said second value from said first register.

5. The semiconductor integrated circuit according to claim 4 , wherein said control circuit outputs said first and second values to said external device in response to an instruction from said external device.

6. The semiconductor integrated circuit according to claim 4 , wherein said external device comprises a debugger performing a debug of said macro.

7. The semiconductor integrated circuit according to claim 4 , wherein said control circuit comprises a TAP controller capable of transitioning to a plurality of states including:

a capture DR state in which said control circuit outputs said first and second values to said external device; and

an update DR state in which said control circuit stores said second value in said second register, said control circuit transitioning to said update DR state after being in said capture DR state, and

wherein said control circuit stores in said second register said second value indicating that said macro has been in said predetermined state, in response to transitioning to said update DR state, in case that said predetermined state of said macro is changed to another state between said capture DR state and said update DR state.

8. The semiconductor integrated circuit according to claim 1 , wherein said predetermined signal comprises a reset signal.

9. The semiconductor integrated circuit according to claim 1 , wherein the first and second registers are not configured as a shift register.

10. An integrated circuit comprising:

a first register configured to receive a signal that causes the first register to store:

a first value indicating whether a macro is in a first state at a first time; and

a second value indicating whether the macro is in first state at a second time that is after the first time; and

a second register configured to store a historical value indicating whether the macro was previously in the first state before the first time,

wherein if the macro was previously in the first state, then the second register retains the historical value as the first value, otherwise the second register stores the historical value as a second value until the signal causes the first register to store the first value and then the second register retains the historical value as the first value.

11. The integrated circuit according to claim 10 , wherein the signal is transmitted by a second macro.

12. The integrated circuit according to claim 11 , wherein the signal comprises a reset signal for causing a state of the macro to transition.