Semiconductor device having trench gate structure
View Patent ↗The present invention provides a vertical MOSFET which has striped trench gate structure which can secure avalanche resistance without increasing Ron. A vertical MOSFET 100 comprises a plurality of gate trenches 7 which is arranged in stripes, an array which is sandwiched with the plurality of gate trenches 7 and includes N + source regions 4 N+ and P + base contact regions 5 P+, and a diode region (anode region 6 P+) which is formed so as to contact with two gate trenches 7 . The N + source regions 4 N+ and the base contact regions 5 P+ are alternately arranged along a longitudinal direction of the gate trench 7 . Size of the diode region (anode region 6 P+) corresponds to at least one of the N + source regions 4 N+ and two of the P + base contact regions 5 P+.
1. A semiconductor device, comprising:
a plurality of gate trenches arranged in stripes;
an array sandwiched with the plurality of gate trenches and including source regions and base contact regions which are alternately arranged along a longitudinal direction of the gate trenches; and
a diode region formed so as to contact with two of the gate trenches which are adjacent to each other,
wherein a size of the diode region is substantially a same size as one of the source regions and two of the base contact regions.
2. The semiconductor device according to claim 1 , wherein the diode region is formed in the array with the source regions and the base contact regions.
3. The semiconductor device according to claim 2 , wherein the diode region is formed between two of the source regions.
4. The semiconductor device according to claim 2 , wherein the array comprises a plurality of ones of the diode region.
5. The semiconductor device according to claim 1 , further comprising another diode region, wherein the diode region and the another diode region are juxtaposed so as to sandwich at least one of the gate trenches therebetween.
6. The semiconductor device according to claim 1 , further comprising:
a gate electrode formed in one of the gate trenches; and
an interlayer insulating film formed on the gate electrode, wherein the interlayer insulating film is formed in the one of the gate trenches.
7. The semiconductor device according to claim 1 , wherein the diode region is juxtaposed to adjacent two of the base contact regions and a source region sandwiched therebetween in an adjacent array.
8. The semiconductor device according to claim 1 , wherein the diode region is juxtaposed to adjacent two of the source regions and the base contact region sandwiched therebetween in an adjacent array.
9. The semiconductor device according to claim 2 , wherein the diode region is formed between said two of the base contact regions in the array.
10. The semiconductor device according to claim 1 , wherein the array is defined as a first array, the semiconductor device further comprising:
a second array comprising a plurality of diode regions and a plurality of base contact regions, each of the plurality of diode regions having a size substantially the same as said one of the source regions and said two of the base contact regions in the first array, each of the plurality of base contact regions having a same size as the base contact regions in the first array, each of the plurality of diode regions and each of the plurality of base contact regions being alternately arranged along the longitudinal direction of the gate trenches in the second array.