Semiconductor circuit
View Patent ↗A semiconductor circuit according to the present invention includes: a differential input section to receive input differential signals; a load resistance section to output a voltage according to a current output by the differential input section; differential signal output terminals to output a differential signal corresponding to the voltage output from the load resistance section; a low-pass filter to extract a direct-current component of the differential signal output from the differential signal output terminals; and a load adjustment section to feed back the direct-current component extracted by the low-pass filter to adjust a resistance value of the load resistance section.
1. A semiconductor circuit, comprising:
a differential input section to receive input differential signals;
a load resistance section to output a voltage according to a current output by the differential input section;
differential signal output terminals to output a differential signal corresponding to the voltage output from the load resistance section;
a low-pass filter to extract a direct-current component of the differential signal output from the differential signal output terminals; and
a load adjustment section to feed back the direct-current component extracted by the low-pass filter to adjust a resistance value of the load resistance section,
wherein the differential input section includes:
a first transistor having a gate receiving one of the input differential signals; and
a second transistor having a gate receiving another of the input differential signals,
wherein the load resistance section includes:
a third transistor connected between a first node connected to a drain of the first transistor, and one of the differential signal output terminals;
a fourth transistor connected between a second node connected to a drain of the second transistor, and another of the differential signal output terminals;
a fifth transistor having a drain connected to the one of the differential signal output terminals, and a gate connected to the second node; and
a sixth transistor having a drain connected to the another of the differential signal output terminals, and a gate connected to the first node.
2. The semiconductor circuit according to claim 1 , further comprising a plurality of stages of differential buffers connected between the differential signal output terminals and the low-pass filter.
3. The semiconductor circuit according to claim 1 , wherein:
the load adjustment section is connected to a ground terminal;
the load resistance section is connected to a power supply voltage terminal; and
the differential input section is connected between the load resistance section and the load adjustment section.
4. The semiconductor circuit according to claim 1 , wherein:
the load adjustment section is connected to a power supply voltage terminal;
the differential input section is connected to a ground terminal; and
the load resistance section is connected between the load adjustment section and the differential input section.
5. The semiconductor circuit according to claim 1 , wherein:
the load resistance section is connected to a power supply voltage terminal;
the differential input section is connected to a ground terminal; and
the load adjustment section is connected in parallel with the differential input section and the ground terminal.
6. The semiconductor circuit according to claim 1 , wherein:
the differential load resistance section is connected to a power supply voltage terminal;
the differential input section is connected to a ground terminal; and
the load adjustment section is connected in parallel with the load resistance section and a power supply voltage terminal.
7. The semiconductor circuit according to claim 1 , wherein the load adjustment section is connected between the differential signal output terminals and a ground terminal.
8. The semiconductor circuit according to claim 1 , wherein the load adjustment section is connected between the differential signal output terminals and a power supply voltage terminal.
9. A semiconductor circuit, comprising:
a differential input section to receive input differential signals;
a load resistance section to output a voltage according to a current output by the differential input section;
differential signal output terminals to output a differential signal corresponding to the voltage output from the load resistance section;
a low-pass filter to extract a direct-current component of the differential signal output from the differential signal output terminals; and
a load adjustment section to feed back the direct-current component extracted by the low-pass filter to adjust a resistance value of the load resistance section,
wherein the load resistance section includes:
a fifth transistor having a drain connected to one of the differential signal output terminals, and a gate connected to another of the differential signal output terminals; and
a sixth transistor having a drain connected to the another of the differential signal output terminals, and a gate connected to the one of the differential signal output terminals.
10. The semiconductor circuit according to claim 9 , further comprising a plurality of stages of differential buffers connected between the differential signal output terminals and the low-pass filter.
11. The semiconductor circuit according to claim 9 , wherein:
the load adjustment section is connected to a ground terminal;
the load resistance section is connected to a power supply voltage terminal; and
the differential input section is connected between the load resistance section and the load adjustment section.
12. The semiconductor circuit according to claim 9 , wherein:
the load adjustment section is connected to a power supply voltage terminal;
the differential input section is connected to a ground terminal; and
the load resistance section is connected between the load adjustment section and the differential input section.
13. The semiconductor circuit according to claim 9 , wherein:
the load resistance section is connected to a power supply voltage terminal;
the differential input section is connected to a ground terminal; and
the load adjustment section is connected in parallel with the differential input section and the ground terminal.
14. The semiconductor circuit according to claim 9 , wherein:
the differential load resistance section is connected to a power supply voltage terminal;
the differential input section is connected to a ground terminal; and
the load adjustment section is connected in parallel with the load resistance section and a power supply voltage terminal.
15. The semiconductor circuit according to claim 9 , wherein the load adjustment section is connected between the differential signal output terminals and a ground terminal.
16. The semiconductor circuit according to claim 9 , wherein the load adjustment section is connected between the differential signal output terminals and a power supply voltage terminal.
17. A semiconductor circuit, comprising:
a differential input section to receive input differential signals;
a load resistance section to output a voltage according to a current output by the differential input section;
differential signal output terminals to output a differential signal corresponding to the voltage output from the load resistance section;
a low-pass filter to extract a direct-current component of the differential signal output from the differential signal output terminals; and
a load adjustment section to feed back the direct-current component extracted by the low-pass filter to adjust a resistance value of the load resistance section,
wherein:
the load adjustment section is connected to a ground terminal;
the load resistance section is connected to a power supply voltage terminal; and
the differential input section is connected between the load resistance section and the load adjustment section.
18. The semiconductor circuit according to claim 17 , further comprising a plurality of stages of differential buffers connected between the differential signal output terminals and the low-pass filter.
19. A semiconductor circuit, comprising:
a differential input section to receive input differential signals;
a load resistance section to output a voltage according to a current output by the differential input section;
differential signal output terminals to output a differential signal corresponding to the voltage output from the load resistance section;
a low-pass filter to extract a direct-current component of the differential signal output from the differential signal output terminals; and
a load adjustment section to feed back the direct-current component extracted by the low-pass filter to adjust a resistance value of the load resistance section,
wherein:
the load adjustment section is connected to a power supply voltage terminal;
the differential input section is connected to a ground terminal; and
the load resistance section is connected between the load adjustment section and the differential input section.
20. The semiconductor circuit according to claim 19 , further comprising a plurality of stages of differential buffers connected between the differential signal output terminals and the low-pass filter.
21. A semiconductor circuit, comprising:
a differential input section to receive input differential signals;
a load resistance section to output a voltage according to a current output by the differential input section;
differential signal output terminals to output a differential signal corresponding to the voltage output from the load resistance section;
a low-pass filter to extract a direct-current component of the differential signal output from the differential signal output terminals; and
a load adjustment section to feed back the direct-current component extracted by the low-pass filter to adjust a resistance value of the load resistance section,
wherein:
the load resistance section is connected to a power supply voltage terminal;
the differential input section is connected to a ground terminal; and
the load adjustment section is connected in parallel with the load resistance section and a power supply voltage terminal.
22. The semiconductor circuit according to claim 21 , further comprising a plurality of stages of differential buffers connected between the differential signal output terminals and the low-pass filter.
23. A semiconductor circuit, comprising:
a differential input section to receive input differential signals;
a load resistance section to output a voltage according to a current output by the differential input section;
differential signal output terminals to output a differential signal corresponding to the voltage output from the load resistance section;
a low-pass filter to extract a direct-current component of the differential signal output from the differential signal output terminals; and
a load adjustment section to feed back the direct-current component extracted by the low-pass filter to adjust a resistance value of the load resistance section,
wherein the load adjustment section is connected between the differential signal output terminals and a power supply voltage terminal.
24. The semiconductor circuit according to claim 23 , further comprising a plurality of stages of differential buffers connected between the differential signal output terminals and the low-pass filter.
25. A semiconductor circuit, comprising:
a differential input section to receive input differential signals;
a load resistance section to output a voltage according to a current output by the differential input section;
differential signal output terminals to output a differential signal corresponding to the voltage output from the load resistance section;
a low-pass filter to extract a direct-current component of the differential signal output from the differential signal output terminals; and
a load adjustment section to feed back the direct-current component extracted by the low-pass filter to adjust a resistance value of the load resistance section,
wherein the differential input section includes:
a first transistor having a gate receiving one of the input differential signals; and
a second transistor having a gate receiving another of the input differential signals,
wherein the load resistance section includes:
the load adjustment section connected between a first node connected to a drain of the first transistor, and one of the differential signal output terminals, and between a second node connected to a drain of the second transistor, and another of the differential signal output terminals;
a fifth transistor having a gate connected to the second node, and a drain connected to the one of the differential signal output terminals; and
a sixth transistor having a gate connected to the first node, and a drain connected to the another of the differential signal output terminals.
26. The semiconductor circuit according to claim 25 , wherein the differential input section is connected between the load resistance section and a ground terminal.
27. The semiconductor circuit according to claim 26 , further comprising a plurality of stages of differential buffers connected between the differential signal output terminals and the low-pass filter.
28. The semiconductor circuit according to claim 25 , further comprising a plurality of stages of differential buffers connected between the differential signal output terminals and the low-pass filter.
29. A semiconductor circuit, comprising:
a differential input section to receive input differential signals;
a load resistance section to output a voltage according to a current output by the differential input section;
differential signal output terminals to output a differential signal corresponding to the voltage output from the load resistance section;
a low-pass filter to extract a direct-current component of the differential signal output from the differential signal output terminals; and
a load adjustment section to feed back the direct-current component extracted by the low-pass filter to adjust a resistance value of the load resistance section,
wherein:
the low-pass filter includes a resistance section and a capacitance section;
the resistance section includes a first transfer gate and a second transfer gate, and the capacitance section includes a gate capacitance of a seventh transistor and a gate capacitance of an eighth transistor;
the first transfer gate has one terminal receiving one of the differential signals output from the differential signal output terminals, and has another terminal connected to a third node;
the second transfer gate has one terminal receiving another of the differential signals output from the differential signal output terminals, and has another terminal connected to a fourth node;
the seventh transistor has a drain and a source that are connected to the third node, and has a gate connected to the fourth node; and
the eighth transistor has a drain and a source that are connected to the fourth node, and has a gate connected to the third node.
30. A semiconductor circuit, comprising:
a differential input section to receive input differential signals;
a load resistance section to output a voltage according to a current output by the differential input section;
differential signal output terminals to output a differential signal corresponding to the voltage output from the load resistance section;
a low-pass filter to extract a direct-current component of the differential signal output from the differential signal output terminals; and
a load adjustment section to feed back the direct-current component extracted by the low-pass filter to adjust a resistance value of the load resistance section,
wherein:
the low-pass filter includes a resistance section and a capacitance section;
the resistance section includes a first transfer gate and a second transfer gate, and the capacitance section includes a gate capacitance of a seventh transistor and a gate capacitance of an eighth transistor;
the first transfer gate has one terminal receiving one of the differential signals output from the differential signal output terminals, and has another terminal connected to a third node;
the second transfer gate has one terminal receiving another of the differential signals output from the differential signal output terminals, and has another terminal connected to a fourth node;
the seventh transistor has a drain and a source that are connected to a ground terminal, and has a gate connected to the third node; and
the eighth transistor has a drain and a source that are connected to the ground terminal, and has a gate connected to the fourth node.