Multi-layered memory devices
A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array.
1. A multi-layered memory device, comprising:
two or more memory units; and
an active circuit unit arranged between each of the two or more memory units, each active circuit unit including a decoder,
wherein the decoder includes at least one of a column decoder and a row decoder,
column address lines connect the column decoder to the two or more memory units through vias, and
row address lines connect the row decoder to the two or more memory units through vias.
2. The multi-layered memory device of claim 1 , wherein each of the memory units includes one or more memory layers.
3. The multi-layered memory device of claim 2 , wherein the memory layers are a cross-point type memory array.
4. The multi-layered memory device of claim 3 , wherein a plurality of sub-arrays are formed on the memory layers.
5. The multi-layered memory device of claim 3 , wherein the cross-point type memory array has a structure in which adjacent memory layers share electrodes.
6. The multi-layered memory device of claim 1 , wherein the active circuit unit is formed on a non-silicon substrate.
7. The multi-layered memory device of claim 6 , wherein the non-silicon substrate is one of a plastic substrate, a glass substrate, a ceramic substrate, an oxide substrate, and a nitride substrate.
8. The multi-layered memory device of claim 1 , wherein the active circuit unit and the two or more memory units are grouped into a memory group, and a plurality of the memory groups are stacked on one another.
9. The multi-layered memory device of claim 1 , wherein the active circuit unit includes a first active circuit unit and a second active circuit unit, the first active circuit unit including the column decoder and the second active circuit unit including the row decoder, at least one of the two or more memory units being connected to each of the first active circuit unit and the second active circuit unit.
10. The multi-layered memory device of claim 1 , further including,
a logic unit formed on a surface of one of the active circuit units and the memory units.
11. The multi-layered memory device of claim 1 , further comprising:
a memory area formed on a substrate, the memory area including the two or more memory units and the active circuit unit;
an input/output chip connected to the memory area and a parallel bus line; and
a serial bus line connecting the input/output chip to a master device.