Evaluation pattern suitable for evaluation of lateral hillock formation

1. An evaluation pattern for evaluation of lateral hillock formation, comprising:

a lattice pattern; and

an isolated metallization,

wherein said lattice pattern includes:

a loop interconnection; and

lattice interconnections laterally and vertically arranged to intersect with one another so that a region surrounded by the loop interconnection is divided into a plurality of sub-regions arranged in rows and columns, wherein a width of said lattice interconnections is narrower than a width of said loop interconnection, and

wherein said isolated metallization is provided in an outmost one of said sub-regions, said outmost one being surrounded by said loop interconnection and corresponding ones of the lattice interconnections.

2. The evaluation pattern according to claim 1 , wherein said isolated metallization is opposed to said loop interconnection across a spacing.

3. The evaluation pattern according to claim 1 , wherein said isolated metallization is provided within each of all the outmost ones of said sub-regions.

4. The evaluation pattern according to claim 1 , wherein said loop-interconnection is electrically connected to a first electrode pad, and

wherein said isolated metallization is electrically connected to a second electrode pad.

5. The evaluation pattern according to claim 4 , further comprising a common interconnection,

wherein said loop interconnection, said lattice interconnections, said isolated metallization and said first and second electrode pads are formed on an upper face of a dielectric film, and

wherein said common interconnection is formed beneath a bottom face of said dielectric film, connected to said isolated metallization through a first via contact formed through said dielectric film, and further connected to said second electrode pad through a second via contact formed through said dielectric film.

6. The evaluation pattern according to claim 1 , wherein said width of said loop interconnections is 10 μm or more.

7. The evaluation pattern according to claim 1 , wherein said width of said lattice interconnections ranges from 0.4 to 1.0 μm.

8. The evaluation pattern according to claim 1 , wherein a width of spacing between said loop interconnection and said isolated metallization ranges from 0.1 to 0.5 μm.

9. The evaluation pattern according to claim 1 , wherein a planar shape of said loop interconnection is square.

10. The evaluation pattern according to claim 9 , wherein a number of rows of said sub-regions is equal to a number of columns of said sub-regions, and

wherein a planar shape of said lattice pattern has two line of symmetry which are orthogonal to each other.

11. The evaluation pattern according to claim 1 , wherein said loop interconnection, said lattice interconnections, and said isolated metallization are formed of aluminum or aluminum alloy.

12. A substrate structure comprising:

a substrate; and

at least one evaluation pattern comprising a lattice pattern and an isolated metallization,

wherein said lattice pattern includes:

a loop interconnection;

lattice interconnections laterally and vertically arranged to intersect with one another so that a region surrounded by the loop interconnection is divided into a plurality of sub-regions arranged in rows and columns, wherein a width of said lattice interconnections are narrower than a width of said loop interconnection, and

wherein said isolated metallization is provided in an outmost one of said sub-regions, said outmost one being surrounded by said loop interconnection and corresponding ones of the lattice interconnections.

13. A method of evaluation of lateral hillock formation, comprising:

providing an evaluation pattern comprising a lattice pattern and an isolated metallization, wherein said lattice pattern includes:

a loop interconnection;

lattice interconnections laterally and vertically arranged to intersect with one another so that a region surrounded by the loop interconnection is divided into a plurality of sub-regions arranged in rows and columns, and

wherein a width of said lattice interconnections are narrower than a width of said loop interconnection, and wherein said isolated metallization is provided in an outmost one of said sub-regions, said outmost one being surrounded by said loop interconnection and corresponding ones of the lattice interconnections;

applying a voltage between said loop interconnection and said isolated metallization; and

detecting electrical conduction between said loop interconnection and said isolated metallization.