Semiconductor device including wiring excellent in impedance matching, and method for designing the same
View Patent ↗A semiconductor device includes an interposer, and a semiconductor chip mounted on the interposer. In a plan view, the interposer includes a first region overlapping the semiconductor chip, and a second region excluding the first region. The interposer includes at least one wiring formed astride the first region and the second region. The cross-sectional area of the wiring in the first region and the cross-sectional area of the wiring in the second region are different from each other.
1. A semiconductor device comprising: an interposer; and a semiconductor chip mounted on the interposer, wherein, in a plan view, the interposer includes a first region overlapping the semiconductor chip, and a second region excluding the first region, and the interposer includes at least one wiring therein, the wiring being formed astride the first region and the second region, wherein a cross-sectional area of the wiring in the first region of the interposer is smaller than a cross-sectional area of the wiring in the second region of the interposer, wherein the semiconductor chip is mounted on the interposer via a mounting material, an upper surface of the semiconductor chip comprising a circuit and a pad, and wherein the wiring in the second region of the interposer and the pad on the semiconductor chip are electrically connected via a wire, wherein a characteristic impedance of the wiring in the first region is substantially equal to a characteristic impedance of the wiring in the second region.
2. The semiconductor device according to claim 1 , wherein a width of the wiring in the first region is narrower than a width of the wiring in the second region.
3. The semiconductor device according to claim 1 , wherein a thickness of the wiring in the first region is thinner than a thickness of the wiring in the second region.
4. The semiconductor device according to claim 3 , wherein a lower surface of the wiring in the first region and a lower surface of the wiring in the second region are on a same plane.
5. The semiconductor device according to claim 1 , wherein the interposer includes a plurality of wiring layers, and
wherein the wiring in the first region and the wiring in the second region are provided in different wiring layers.
6. The semiconductor device according to claim 1 , wherein the semiconductor chip is mounted on the interposer via a solder resist.
7. The semiconductor device according to claim 1 , further comprising a printed wiring board with the interposer mounted thereon.
8. The semiconductor device according to claim 1 , wherein the semiconductor chip comprises an LSI (large-scale integration) including a logic circuit function.
9. The semiconductor device according to claim 1 , wherein, in the cross-sectional area, a border of the first region overlaps with an edge of the semiconductor chip.
10. The semiconductor device according to claim 1 , wherein a solder resist is disposed between the wiring and the mounting material.
11. The semiconductor device according to claim 1 , wherein a solder resist is disposed on an upper surface of the wiring in the first region and in the second region, said wire abutting an unexposed portion of the wiring in the second region.
12. The semiconductor device according to claim 1 , wherein a lower surface of the wiring in the first region is co-planner with a lower surface of the wiring in the second region.