Simplified run-time program translation for emulating complex processor pipelines
View Patent ↗Simplification of run-time program translation for emulating complex processor pipelines is disclosed. Dynamic pipeline states are moved into a cache lookup process leaving a code translation process to deal only with static pipeline states. With dynamic pipeline states removed from the translation process, translation becomes more simple and efficient like that of a non-pipelined processor.
1. A method for program translation in a processor pipeline, the method comprising:
determining a current target address and pipeline signature, the pipeline signature including a state of the processor pipeline, the pipeline signature allowing one program address to correspond to multiple cached translations, each cached translation keyed by a different pipeline signature;
requesting a translation based at least in part on the current target address and the pipeline signature, the translation including instructions translated for a processor; and
generating the translation when the translation is unavailable, the translation valid for only a single address and pipeline signature pair.
2. The method of claim 1 , wherein the target address and pipeline signature are looked up in a hash table.
3. The method of claim 1 , wherein the target address and pipeline signature are static values.
4. The method of claim 1 , further comprising saving the translation in a translation cache.
5. The method of claim 4 , further comprising executing the translation.
6. The method of claim 1 , wherein the translation includes translating instructions to an instruction set of the processor.
7. A method for program translation in a processor pipeline, the method comprising:
determining a current target address and pipeline signature, the pipeline signature including a state of the processor pipeline, the pipeline signature allowing one program address to correspond to multiple cached translations, each cached translation keyed by a different pipeline signature;
requesting a translation based at least in part on the current target address and the pipeline signature, the translation including instructions translated for a processor; and
executing the translation when the translation is unavailable, the translation valid for only a single address and pipeline signature pair.
8. The method of claim 7 , wherein the target address and pipeline signature are looked up in a hash table.
9. The method of claim 7 , wherein the target address and pipeline signature are static values.
10. A processor pipeline translation method, comprising:
decoding a current target address and pipeline signature, the pipeline signature including a state of a processor pipeline, the pipeline signature allowing one program address to correspond to multiple cached translations, each cached translation keyed by a different pipeline signature;
checking for a stall;
calling a code generation function to translate instructions for a processor for lower and upper instructions; and
updating an address pipeline signature pair, for which a generated translation is valid for only the address pipeline signature pair.
11. The method of claim 10 , wherein the code generation function maps required input registers.
12. The method of claim 11 , wherein the mapped input registers are maintained in a temporary register.
13. The method of claim 12 , further comprising creating a record for a write back operation.
14. The method of claim 11 , further comprising writing back the mapped input registers to a register file.
15. The method of claim 10 , wherein the stall is checked with respect to VF and VI stalls.
16. The method of claim 15 , wherein the stall is checked using current VFRD, VIRU, and VIS[ ] information.